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Integrated Device Technology Electronic Components Datasheet



ICS853S310I

1-to-8 Differential-to- 3.3V LVPECL/ECL Fanout Buffer



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ICS853S310I pdf
Low Skew, 1-to-8 Differential-to-
3.3V LVPECL/ECL Fanout Buffer
ICS853S310I
DATA SHEET
General Description
The ICS853S310I is a low skew, high performance 1-to-8
Differential-to-3.3V LVPECL/ECL Fanout Buffer. The PCLKx,
nPCLKx pairs can accept LVPECL, LVDS, CML and SSTL
differential input levels. The ICS853S310I is characterized to operate
from a 3.3V power supply. Guaranteed output and part-to-part skew
characteristics make the ICS853S310I ideal for those clock
distribution applications demanding well defined performance and
repeatability.
Features
Eight differential 3.3V LVPECL/ECL outputs
Two selectable differential input pairs
PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: 2GHz
Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nPCLKx input
Output skew: 20ps (typical)
Propagation delay: 825ps (typical)
Additive phase jitter, RMS: 0.14ps (typical)
LVPECL mode operating voltage supply range:
VCC = 3.0V to 3.8V, VEE = 0V
ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.0V to -3.8V
-40°C to 85°C ambient operating temperature
Available lead-free (RoHS 6) package
Block Diagram
PCLK0 Pulldown
nPCLK0 Pullup/Pulldown
PCLK1 Pulldown
nPCLK1 Pullup/Pulldown
0
1
CLK_SEL Pulldown
VBB
Pin Assignment
Q0
nQ0 25 24 23 22 21 20 19
Q1
VEE 26
18 Q3
nQ1 CLK_SEL 27
17 nQ3
Q2 PCLK0 28
16 Q4
nQ2
VCC 1
15 VCCO
Q3 nPCLK0 2
14 nQ4
nQ3
VBB 3
13 Q5
PCLK1 4
Q4
12 nQ5
5 6 7 8 9 10 11
nQ4
Q5
nQ5
ICS853S310I
Q6
nQ6 28-Lead PLCC
11.6mm x 11.4mm x 4.1mm package body
Q7 V Package
nQ7 Top View
ICS853S310CVI REVISION A NOVEMBER 17, 2010
1
©2010 Integrated Device Technology, Inc.



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ICS853S310I pdf
ICS853S310I Data Sheet
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7, 9
8, 15, 22
10, 11
12, 13
14, 16
17, 18
19, 20
21, 23
24, 25
26
27
28
Name
VCC
nPCLK0
VBB
PCLK1
nPCLK1
nc
nQ7, Q7
VCCO
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
VEE
CLK_SEL
PCLK0
Type
Power
Input
Pullup/
Pulldown
Output
Input
Pulldown
Input
Pullup/
Pulldown
Unused
Output
Power
Output
Output
Output
Output
Output
Output
Output
Power
Input
Pulldown
Input
Pulldown
Description
Positive supply pin.
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Bias voltage to be connected for single-ended applications.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. VCC/2 default when left floating.
No connect
Differential output pair. LVPECL/ECL interface levels.
Output supply pins.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Negative supply pin.
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When LOW,
selects PCLK0, nPCLK0 inputs. LVPECL single-ended interface levels. Also
accepts standard LVCMOS input levels.
Non-inverting differential LVPECL clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
RPULLDOWN Input Pulldown Resistor
RVCC/2
Pullup/Pulldown Resistors
Test Conditions
Minimum
Typical
75
50
Maximum
Units
k
k
ICS853S310CVI REVISION A NOVEMBER 17, 2010
2
©2010 Integrated Device Technology, Inc.



Part Number ICS853S310I
Description 1-to-8 Differential-to- 3.3V LVPECL/ECL Fanout Buffer
Maker Integrated Device Technology - Integrated Device Technology
Total Page 17 Pages
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