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ICS853S013I

LVPECL/ECL Fanout Buffer


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ICS853S013I pdf
Low Skew, Dual, 1-to-3, Differential-to-2.5V,
3.3V LVPECL/ECL Fanout Buffer
ICS853S013I
DATASHEET
General Description
The ICS853S013I is a low skew, high performance dual 1-to-3
Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer. The
ICS853S013I operates with a positive or negative power supply at
2.5V or 3.3V. Guaranteed output and part-to-part skew
characteristics make the ICS853S013I ideal for those clock
distribution applications demanding well defined performance and
repeatability.
Features
Two differential LVPECL/ECL bank outputs
Two differential LVPECL clock input pairs
PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Output frequency: 2GHz (maximum)
Translates any single-ended input signal to LVPECL levels with
resistor bias on nPCLKx input
Bank skew: 60ps (maximum)
Part-to-part skew: 190ps (maximum)
Propagation delay: 460ps (maximum)
Additive phase jitter, RMS: 0.05ps (typical)
LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
PCLKA Pulldown
nPCLKA Pullup/Pulldown
PCLKB Pulldown
nPCLKB Pullup/Pulldown
QA0
nQA0
QA1
nQA1
QA2
nQA2
QB0
nQB0
QB1
nQB1
QB2
nQB2
Pin Assignment
nQA0
QA0
VCC
PCLKA
nPCLKA
PCLKB
nPCLKB
VCC
nQB0
QB0
1
2
3
4
5
6
7
8
9
10
20 QA1
19 nQA1
18 QA2
17 nQA2
16 VCC
15 QB2
14 nQB2
13 QB1
12 nQB1
11 VEE
ICS853S013I
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm package body
M Package
Top View
ICS853S013AMI REVISION A AUGUST 20, 2010
1
©2010 Integrated Device Technology, Inc.



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ICS853S013I pdf
ICS853S013I Data Sheet
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2
3, 8, 16
4
5
6
7
9, 10
11
12, 13
14, 15
17, 18
19, 20
Name
nQA0, QA0
VCC
PCLKA
nPCLKA
PCLKB
nPCLKB
nQB0, QB0
VEE
nQB1, QB1
nQB2, QB2
nQA2, QA2
nQA1, QA1
Type
Output
Power
Input
Input
Input
Input
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Output
Power
Output
Output
Output
Output
Description
Differential output pair. LVPECL interface levels.
Power supply pins.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Differential output pair. LVPECL interface levels.
Negative supply pin.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
RPULLDOWN Input Pulldown Resistor
RVCC/2
Pullup/Pulldown Resistors
Test Conditions
Minimum
Typical
75
50
Maximum
Units
k
k
Function Table
Table 3. Clock Input Function Table
Inputs
PCLKA or PCLKB
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nPCLKA or nPCLKB
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Outputs
QA[0:2],
QB[0:2]
nQA[0:2],
nQB[0:2]
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
NOTE 1: Please refer to the Application Information, Wiring the Differential Input to Accept Single Ended Levels.
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
ICS853S013AMI REVISION A AUGUST 20, 2010
2
©2010 Integrated Device Technology, Inc.



Part Number ICS853S013I
Description LVPECL/ECL Fanout Buffer
Maker IDT - IDT
Total Page 16 Pages
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