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ICS853S011CI

LVPECL/ECL Fanout Buffer



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ICS853S011CI pdf
Low Skew, 1-to-2, Differential-to-2.5V, 3.3V ICS853S011CI
LVPECL/ECL Fanout Buffer
DATA SHEET
General Description
The ICS853S011CI is a low skew, high performance 1-to-2
Differential-to-2.5V/3.3V LVPECL/ECL Fanout Buffer. The
ICS853S011CI is characterized to operate from either a 2.5V or a
3.3V power supply. Guaranteed output and part-to-part skew
characteristics make the ICS853S011CI ideal for those clock
distribution applications demanding well defined performance and
repeatability.
Features
Two differential 2.5V, 3.3V LVPECL/ECL outputs
One differential PCLK, nPCLK input pair
PCLK, nPCLK pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: >2.5GHz
Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nPCLK input
Output skew: 20ps (maximum)
Part-to-part skew: 150ps (maximum)
Propagation delay: 330ps (maximum)
LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Block Diagram
PCLK Pulldown
nPCLK Pullup/Pulldown
Q0
nQ0
Q1
nQ1
ICS853S011CGI REVISION A JULY 16, 2013
Pin Assignment
Q0 1
nQ0 2
Q1 3
nQ1 4
8 VCC
7 PCLK
6 nPCLK
5 VEE
ICS853S011CI
8-Lead SOIC, 150MIL
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
8-Lead TSSOP, 118MIL
3.0mm x 3.0mm x 0.97mm package body
G Package
Top View
1 ©2013 Integrated Device Technology, Inc.



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ICS853S011CI pdf
ICS853S011CI Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2
Q0, nQ0
Output
Differential output pair. LVPECL/ECL interface levels.
3, 4
Q1, nQ1
Output
Differential output pair. LVPECL/ECL interface levels.
5 VEE Power
Negative supply pin.
6
nPCLK
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. When left floating, defaults to 2/3 VCC.
7
PCLK
Input
Pulldown Non-inverting differential LVPECL clock input.
8 VCC Power
Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
RPULLDOWN Input Pulldown Resistor
RPULLUP
Pullup Resistors
Test Conditions
Minimum
Typical
75
37
Maximum
Units
k
k
ICS853S011CGI REVISION A JULY 16, 2013
2
©2013 Integrated Device Technology, Inc.



Part Number ICS853S011CI
Description LVPECL/ECL Fanout Buffer
Maker IDT - IDT
Total Page 19 Pages
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