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ICS8432I-51

CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER



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ICS8432I-51 pdf
700wMwwH.DZata,SCheYet4RU.ScoTmAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
ICS8432I-51
GENERAL DESCRIPTION
The ICS8432I-51 is a general purpose, dual out-
ICS put Crystal-to-3.3V Differential LVPECL High Fre-
HiPerClockS™ q u e n c y S y n t h e s i z e r a n d a m e m b e r o f t h e
HiPerClockS™ family of High Performance Clock
Solutions from IDT. The ICS8432I-51 has a select-
able REF_CLK or crystal input. The VCO operates at a fre-
quency range of 250MHz to 700MHz. The VCO frequency is
programmed in steps equal to the value of the input reference
or crystal frequency. The VCO and output frequency can be
programmed using the serial or parallel interface to the con-
figuration logic. The low phase noise characteristics of the
ICS8432I-51 make it an ideal clock source for Gigabit Ethernet,
Fibre Channel 1 and 2, and Infiniband applications.
FEATURES
Dual differential 3.3V LVPECL outputs
Selectable crystal oscillator interface or
LVCMOS/LVTTL TEST_CLK
Output frequency range: 31.25MHz to 700MHz
Crystal input frequency range: 12MHz to 25MHz
VCO range: 250MHz to 700MHz
Parallel or serial interface for programming counter and
output dividers
RMS period jitter: 3.5ps (maximum)
Cycle-to-cycle jitter: 40ps (maximum)
3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
VCO_SEL
XTAL_SEL
REF_CLK
XTAL1
XTAL2
OSC
0
1
MR
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
PLL
PHASE DETECTOR
VCO
0 ÷1
÷2
÷M
÷4
1 ÷8
CONFIGURATION
INTERFACE
LOGIC
IDT/ ICS3.3V LVPECL FREQUENCY SYNTHESIZER
FOUT0
nFOUT0
FOUT1
nFOUT1
TEST
1
32 31 30 29 28 27 26 25
M5 1
M6 2
M7 3
M8 4
N0 5
N1 6
nc 7
VEE 8
ICS8432I-51
24 XTAL_OUT
23 REF_CLK
22 XTAL_SEL
21 VCCA
20 S_LOAD
19 S_DATA
18 S_CLOCK
17 MR
9 10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
32-Lead VFQFN
5mm x 5mm x 0.95m package body
K Package
Top View
ICS8432BYI-51 REV. A SEPTEMBER 24, 2007



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ICS8432I-51 pdf
ICS8432I-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
FUNCwTwIwO.NDAatLaSDheEeSt4CUR.cIPomTION
NOTE: The functional description that follows describes opera-
tion using a 25MHz crystal. Valid PLL loop divider values for dif-
ferent crystal or input frequencies are defined in the Input
Frequency Characteristics, Table 5, NOTE 1.
The ICS8432I-51 features a fully integrated PLL and therefore,
requires no external components for setting the loop bandwidth.
A fundamental crystal is used as the input to the on-chip oscilla-
tor. The output of the oscillator is fed into the phase detector.
A 25MHz crystal provides a 25MHz phase detector reference
frequency. The VCO of the PLL operates over a range of 250MHz
to 700MHz. The output of the M divider is also applied to the
phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high
or too low), the PLL will not achieve lock. The output of the VCO is
scaled by a divider prior to being sent to each of the LVPECL output
buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8432I-51 support two in-
put modes to program the M divider and N output divider. The
two input operational modes are parallel and serial. Figure 1 shows
the timing diagram for each mode. In parallel mode, the nP_LOAD
input is initially LOW. The data on inputs M0 through M8 and N0
and N1 is passed directly to the M divider and N output divider.
On the LOW-to-HIGH transition of the nP_LOAD input, the data
is latched and the M divider remains loaded until the next LOW
transition on nP_LOAD or until a serial event occurs. As a result,
the M and N bits can be hardwired to set the M divider and
N output divider to a specific default state that will automatically
occur during power-up. The TEST output is LOW when operating
in the parallel input mode. The relationship between the VCO
frequency, the crystal frequency and the M divider is defined as
follows: fVCO = fxtal x M
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table.
Valid M values for which the PLL will achieve lock for a 25MHz
reference are defined as 10 M 28. The frequency out is de-
fined as follows: FOUT = fVCO = fxtal x M
NN
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits
with the rising edge of S_CLOCK. The contents of the shift reg-ister
are loaded into the M divider and N output divider when S_LOAD
transitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD. If
S_LOAD is held HIGH, data at the S_DATA input is passed directly
to the M divider and N output divider on each ris-ing edge of
S_CLOCK. The serial mode can be used to program the M and N
bits and test bits T1 and T0. The internal registers T0 and T1 deter-
mine the state of the TEST output as follows:
T1 T0
00
01
10
11
TEST Output
LOW
S_Data, Shift Register Input
Output of M divider
CMOS Fout
S_CLOCK
SERIAL LOADING
S_DATA
S_LOAD
T 1 T0 *NULL N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M 0
tt
SH
nP_LOAD
M0:M8, N0:N1
M, N
PARALLEL LOADING
t
S
nP_LOAD
S_LOAD
tt
SH
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
IDT/ ICS3.3V LVPECL FREQUENCY SYNTHESIZER
2
ICS8432BYI-51 REV. A SEPTEMBER 24, 2007



Part Number ICS8432I-51
Description CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Maker Integrated Device Technology - Integrated Device Technology
Total Page 20 Pages
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