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ICS843004-125

FemtoClock Crystal-to-3.3V LVPECL Frequency Synthesizer



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ICS843004-125 pdf
FemtoClock™ Crystal-to-3.3V
ICS843004-125
LVPECL Frequency Synthesizer
ADVANCE INFORMATION
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DATA SHEET
GENERAL DESCRIPTION
The ICS843004-125 is a 4 output LVPECL Syn-
ICS thesizer optimized to generate Ethernet reference
HiPerClockS™ c l o c k f r e q u e n c i e s a n d i s a m e m b e r o f t h e
HiPerClocksTM family of high performance clock
solutions from IDT. The ICS843004-125 uses
IDT’s 3rd generation low phase noise VCO technology and can
achieve 1ps or lower typical rms phase jitter, easily meeting
Ethernet jitter requirements. The ICS843004-125 is packaged
in a small 24-pin TSSOP package.
FEATURES
• Four 3.3V LVPECL output pairs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Crystal oscillator designed for 25MHz, 18pF parallel resonant
crystal
• Supports the following output frequency: 125MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.58ps (typical)
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
FREQUENCY SELECT FUNCTION TABLE
M Divider Value
25
Inputs
N Divider Value
5
M/N Divider Value
5
Output Frequency (MHz)
(25MHz Ref.)
125
BLOCK DIAGRAM
nPLL_SEL Pulldown
REF_CLK Pulldown
25MHz
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL Pulldown
1
0
Phase
Detector
VCO
625MHz
(w/25MHz
Reference)
1
0
÷5
M = 25 (fixed)
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
MR Pulldown
PIN ASSIGNMENT
nQ1
Q1
VCCo
Q0
1
2
3
4
24 nQ2
23 Q2
22 VCCO
21 Q3
nQ0
MR
nPLL_SEL
nc
VCCA
nc
VCC
nc
5
6
7
8
9
10
11
12
20 nQ3
19 VEE
18 VCC
17 nXTAL_SEL
16 REF_CLK
15 VEE
14 XTAL_IN
13 XTAL_OUT
ICS843004-125
24-Lead TSSOP
4.40mm x 7.8mm x 0.925mm
package body
G Package
Top View
ICS843004AG-125 REVISION A JUNE 3, 2009
1
©2009 Integrated Device Technology, Inc.



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ICS843004-125 pdf
ICS43004-125 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
www.DataSheet4U.com
TABLE 1. PIN DESCRIPTIONS
Number Name
Type
Description
1, 2 nQ1, Q1 Output
Differential output pair. LVPECL interface levels.
3, 22
4, 5
VCCO
Q0, nQ0
Power
Ouput
Output supply pins.
Differential output pair. LVPECL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing
6
MR
Input
Pulldown
the true outputs Qx to go low and the inverted outputs nQx to go high. When logic
LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
Selects between the PLL and REF_CLK as input to the dividers. When LOW, selects
7 nPLL_SEL Input Pulldown PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass).
LVCMOS/LVTTL interface levels.
8, 10, 12
nc Unused
No connect.
9
11, 18
13, 14
VCCA
VCC
XTAL_OUT,
XTAL_IN
Power
Power
Input
Analog supply pin.
Core supply pins.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input.
15, 19
16
VEE
REF_CLK
Power
Negative supply pins.
Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Selects between crystal or REF_CLK inputs as the the PLL Reference source.
17 nXTAL_SEL Input Pulldown Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.
LVCMOS/LVTTL interface levels.
20, 21 nQ3, Q3 Output
Differential output pair. LVPECL interface levels.
23, 24 Q2, nQ2 Output
Differential output pair. LVPECL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
RPULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
ICS843004AG-125 REVISION A JUNE 3, 2009
2
©2009 Integrated Device Technology, Inc.



Part Number ICS843004-125
Description FemtoClock Crystal-to-3.3V LVPECL Frequency Synthesizer
Maker Integrated Device Technology - Integrated Device Technology
Total Page 14 Pages
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