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ICS843002I-72

FEMTOCLOCKS VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR



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FEMTOCLOCKS™ VCXO BASED WCDMA
CLOCK GENERATOR/JITTER ATTENUATOR
ICS843002I-72
GENERAL DESCRIPTION
The ICS843002I-72 is a member of the
ICS HiperClockS™ family of high performance clock
HiPerClockS™ solutions from IDT. The ICS843002I-72 is a
PLL based synchronous clock generator that is
optimized for WCDMA channel card applications
where jitter attenuation and frequency translation is needed.
The device contains two internal PLL stages that are cascaded
in series. The first PLL stage uses a VCXO which is optimized
to provide reference clock jitter attenuation and to be jitter
tolerant, and to provide a stable reference clock for the second
PLL stage. The second PLL stage provides additional frequency
multiplication (x32), and it maintains low output jitter by using a
low phase noise FemtoClock™ VCO. The device performance
and the PLL multiplication ratios are optimized to support
WCDMA applications. The VCXO requires the use of an
external, inexpensive pullable crystal. VCXO PLL uses external
passive loop filter components which are used to optimize the
PLL loop bandwidth and damping characteristics for the given
application.
FEATURES
Two differential LVPECL outputs
CLK input accepts the following input levels:
LVCMOS or LVTTL levels
Output frequency: 122.88MHz (typical)
FemtoClock VCO frequency range: 490MHz - 680MHz
RMS phase jitter @ 122.88MHz, using a 19.2MHz crystal
(1.875MHz to 10MHz): 0.49ps (typical)
Deterministic jitter: 30fs (typical)
Random jitter, RMS: 2.2ps (typical)
Full 3.3V or mixed 3.3V core/2.5V output supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
The ICS843002I-72 can accept a single-ended input. LOCK_DT
reports the lock status of VCXO PLL loop. If the reference clock
input is lost, it will set LOCK_DT to logic LOW.
Typical ICS843002I-72 configuration in WCDMA Systems:
19.2MHz pullable crystal
Input Reference clock frequency: 3.84MHz
Output clock frequency: 122.88MHz
PIN ASSIGNMENT
IDT/ ICSWCDMA CLOCK GENERATOR/JITTER ATTENUATOR
1
LF1
LF0
ISET
VCC
VCC
VEE
VEE
CLK
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
LOCK_DT
VEE
VCC
VCCO
VCCO
nQ1
Q1
VEE
ICS843002I-72
32-Lead VFQFN
5mm x 5mm x 0.925 package body
K Package
Top View
ICS843002BKI-72 REV. A NOVEMBER 21, 2007



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ICS843002I-72 pdf
ICS843002I-72
FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
BLOCK DIAGRAM
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3.84MHz
CLK
Pulldown
XTAL_IN
19.2MHz
Pullable Xtal
XTAL_OUT
External
Loop
LF0
Components LF1
ISET
LOCK_DT
VCXO
LF
÷5
FemtoClock
x32
Phase
Detect
Charge
Pump
NOTE 1: 19.2MHz pullable crystal shown is typical for WCDMA device applications.
122.88MHz
Q0
nQ0
Q1
nQ1
Pulldown nOE
IDT/ ICSWCDMA CLOCK GENERATOR/JITTER ATTENUATOR
2
ICS843002BKI-72 REV. A NOVEMBER 21, 2007



Part Number ICS843002I-72
Description FEMTOCLOCKS VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
Maker Integrated Device Technology - Integrated Device Technology
Total Page 18 Pages
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