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ICS843002I-41

700MHZ FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR



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ICS843002I-41 pdf
700MHZ, FEMTOCLOCKTM VCXO BASED
SONET/SDH JITTER ATTENUATOR
General Description
The ICS843002I-41 is a member of the
ICS HiperClockS™ family of high performance clock
HiPerClockS™ solutions from IDT. The ICS843002I-41 is a PLL
based synchronous clock generator that is
optimized for SONET/SDH line card applications
where jitter attenuation and frequency translation is needed. The
device contains two internal PLL stages that are cascaded in
series. The first PLL stage uses a VCXO which is optimized to
provide reference clock jitter attenuation and to be jitter tolerant,
and to provide a stable reference clock for the 2nd PLL stage
(typically 19.44MHz). The second PLL stage provides additional
frequency multiplication (x32), and it maintains low output jitter by
using a low phase noise FemtoClock™VCO. PLL multiplication
ratios are selected from internal lookup tables using device input
selection pins. The device performance and the PLL multiplication
ratios are optimized to support non-FEC (non-Forward Error
Correction) SONET/SDH applications with rates up to OC-48
(SONET) or STM-16 (SDH). The VCXO requires the use of an
external, inexpensive pullable crystal. VCXO PLL uses external
passive loop filter components which are used to optimize the PLL
loop bandwidth and damping characteristics for the given
line card application.
The ICS843002I-41 includes two clock input ports. Each one can
accept either a single-ended or differential input. Each input port
also includes an activity detector circuit, which reports input clock
activity through the LOR0 and LOR1 logic output pins. The two
input ports feed an input selection mux. “Hitless switching” is
accomplished through proper filter tuning. Jitter transfer and
wander characteristics are influenced by loop filter tuning, and
phase transient performance is influenced by both loop filter
tuning and alignment error between the two reference clocks.
Typical ICS843002I-41 configuration in SONET/SDH Systems:
VCXO 19.44MHz crystal
Loop bandwidth: 50Hz - 250Hz
Input Reference clock frequency selections:
19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz,
622.08MHz
Output clock frequency selections:
19.44MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz,
Hi-Z
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ICS843002I-41
Features
Two Differential LVPECL outputs
Selectable CLKx, nCLKx differential input pairs
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or
single-ended LVCMOS or LVTTL levels
Maximum output frequency: 700MHz
FemtoClock VCO frequency range: 560MHz - 700MHz
RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal
(12kHz to 20MHz): 0.81ps (typical)
Full 3.3V or mixed 3.3V core/2.5V output operating supply
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
32 31 30 29 28 27 26 25
LF1
LF0
ISET
VCC
CLK0
nCLK0
CLK_SEL
QA_SEL2
1
2
3
4
5
6
7
8
24 LOR0
23 LOR1
22 nc
21 VCCO_LVCMOS
20 VCCO_LVPECL
19 nQB
18 QB
17 VEE
9 10 11 12 13 14 15 16
ICS843002I-41
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
1
ICS843002AKI-41 REV. A OCTOBER 25, 2007



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ICS843002I-41 pdf
ICS843002I-41
700MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
www.DataSheet4U.com
Block Diagram
VCCO_LVCMOS
CLK1
nCLK1
LOR1
CLK0
nCLK0
LOR0
CLK_SEL
ICS843002I-41
Activity
Detector
Activity
Detector
1
0
R_SEL2:0 3
R Divider =
1, 2, 4, 8,
16 or 32
Divide
by 32
External
Loop
Components
19.44 MHz
Pullable
xtal
ISET
LF0 LF1
Phase
Detector
Charge
Pump
and Loop
Filter
19.44 MHz
VCXO
Divide
by 32
VCXO Jitter Attenuation PLL
622.08 MHz
110 FemtoClock
PLL
111
110 x32
Cx Divider =
1,2,4,8,16,32,
HiZ or Disable
111
Cx Divider =
1,2,4,8,16,32,
HiZ or Disable
VCCO_PECL
QA
nQA
3 QA_SEL2:0
QB
nQB
3 QB_SEL2:0
NOTE: 19.44MHz VCXO crystal shown is typical for SONET/SDH device applications.
IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
2
ICS843002AKI-41 REV. A OCTOBER 25, 2007



Part Number ICS843002I-41
Description 700MHZ FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR
Maker Integrated Device Technology - Integrated Device Technology
Total Page 23 Pages
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