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ICS8430-62

2.5V Differential LVPECL Frequency Synthesizer



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ICS8430-62 pdf
500MHz, Crystal-to-3.3V, 2.5V
ICS8430-62
Differential LVPECL Frequency Synthesizer
DATASHEET
General Description
The ICS8430-62 is a general purpose, dual output
ICS Crystal-to-3.3V, 2.5V Differential LVPECL High
HiPerClockS™ Frequency Synthesizer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from IDT. The ICS8430-62 has a selectable
REF_CLK or crystal inputs. The VCO operates at a frequency range
of 250MHz to 500MHz. The VCO frequency is programmed in steps
equal to the value of the input reference or crystal frequency. The
VCO and output frequency can be programmed using the serial or
parallel interfaces to the configuration logic. Frequency steps as
swmwawll.aDsa1taMSHhezecta4Un.bceomachieved using a 16MHz crystal or REF_CLK.
Block Diagram
Features
Dual differential 3.3V or 2.5V LVPECL outputs
Selectable crystal oscillator interface or LVCMOS/LVTTL
REF_CLK
Output frequency range: 20.83MHz to 500MHz
Crystal input frequency range: 14MHz to 27MHz
VCO range: 250MHz to 500MHz
Parallel or serial interface for programming counter
and output dividers
RMS period jitter: 5ps (maximum)
Cycle-to-cycle jitter: 35ps (maximum)
Full 3.3V or 3.3V core/2.5V output supply
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
VCO_SEL Pullup
XTAL_SEL Pullup
REF_CLK Pulldown
0
XTAL_IN
XTAL_OUT
OSC 1
÷16
MR Pulldown
PLL
Phase Detector
VCO
÷M
÷1
÷1.5
÷2
÷3
÷4
÷6
0
÷8
÷12
1
S_LOAD Pulldown
S_DATA Pulldown
S_CLOCK Pulldown
nP_LOAD Pulldown
M0:M8
N0:N2
9
3
Configuration
Interface Logic
Pin Assignment
FOUT0
nFOUT0
FOUT1
nFOUT1
TEST
32 31 30 29 28 27 26 25
M5 1
24 XTAL_OUT
M6 2
23 REF_CLK
M7 3
22 XTAL_SEL
M8 4
21 VCCA
N0 5
20 S_LOAD
N1 6
19 S_DATA
N2 7
18 S_CLOCK
VEE 8
17 MR
9 10 11 12 13 14 15 16
ICS8430-62
32 Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8430AY-62 REVISION A JULY 2, 2009
1
©2009 Integrated Device Technology, Inc.



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ICS8430-62 pdf
ICS8430-62 Datasheet
500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Functional Description
NOTE: The functional description that follows describes operation
using a 16MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 5, NOTE 1.
The ICS8430-62 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth. A
parallel-resonant, fundamental crystal is used as the input to the
on-chip oscillator. The output of the oscillator is divided by 16 prior to
the phase detector. With a 16MHz crystal, this provides a 1MHz
reference frequency. The VCO of the PLL operates over a range of
250MHz to 500MHz. The output of the M divider is also applied to the
phase detector.
The phase detector and the M divider force the VCO output
fwrewqwue.DnacytatSohbeeetM4Ut.icmoems the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high
or too low), the PLL will not achieve lock. The output of the VCO is
scaled by a divider prior to being sent to each of the LVPECL output
buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8430-62 support two input
modes to program the M divider and N output divider. The two input
operational modes are parallel and serial. Figure 1 shows the timing
diagram for each mode. In parallel mode, the nP_LOAD input is
initially LOW. The data on inputs M0 through M8 and N0 through N2
is passed directly to the M divider and N output divider. On the
LOW-to-HIGH transition of the nP_LOAD input, the data is latched
and the M divider remains loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. As a result, the M and N bits
can be hard-wired to set the M divider and N output divider to a
specific default state that will automatically occur during power-up.
The TEST output is LOW when operating in the parallel input mode.
The relationship between the VCO frequency, the crystal frequency
and the M divider is defined as follows:
fVCO = fXTAL x M
16
The M value and the required values of M0 through M8 are shown in
Table 3B, Programmable VCO Frequency Function Table. Valid M
values for which the PLL will achieve lock for a 16MHz reference are
defined as 250 M 500. The frequency out is defined as follows:
fout = fVCO = fXTAL x M
N 16 N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider and N output divider when S_LOAD
transitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD. If
S_LOAD is held HIGH, data at the S_DATA input is passed directly to
the M divider and N output divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and N bits and test
bits T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
T1 T0 TEST Output
0 0 LOW
0 1 S_DATA, Shift Register Input
1 0 Output of M Divider
1 1 Do Not Use
S_CLOCK
SERIAL LOADING
S_DATA
S_LOAD
T1 T0 N2 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0
tt
SH
nP_LOAD
M0:M8, N0:N2
M, N
PARALLEL LOADING
t
S
nP_LOAD
S_LOAD
Figure 1. Parallel & Serial Load Operations
tt
SH
Time
ICS8430AY-62 REVISION A JULY 2, 2009
2
©2009 Integrated Device Technology, Inc.



Part Number ICS8430-62
Description 2.5V Differential LVPECL Frequency Synthesizer
Maker Integrated Device Technology - Integrated Device Technology
Total Page 23 Pages
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