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Integrated Device Technology Electronic Components Datasheet



ICS8344I-01

1-TO-24 DIFFERENTIAL -TO-LVCMOS/LVTTL FANOUT BUFFER



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ICS8344I-01 pdf
PRELIMINARY
LOW SKEW, 1-TO-24 DIFFERENTIAL-
TO-LVCMOS/LVTTL FANOUT BUFFER
ICS8344I-01
GENERAL DESCRIPTION
The ICS8344I-01 is a low voltage, low skew
ICS fanout buffer and a member of the HiPerClockS ™
HiPerClockS™ family of High Performance Clock Solutions from
IDT. The ICS8344I-01 has two selectable clock in-
puts. The CLKx, nCLKx pairs can accept most
standard differential input levels. The ICS8344I-01 is designed
to translate any differential signal level to LVCMOS/LVTTL lev-
els. The low impedance LVCMOS/LVTTL outputs are designed
www.DatatSohederti4vUe.c5o0mΩ series or parallel terminated transmission lines.
The effective fanout can be increased to 48 by utilizing the
ability of the outputs to drive two series terminated lines.
Redundant clock applications can make use of the dual clock
inputs which also facilitate board level testing. The clock
enable is internally synchronized to eliminate runt pulses on
the outputs during asynchronous assertion/deassertion of the
clock enable pin. The outputs are driven low when disabled.
The ICS8344I-01 is characterized at full 3.3V, full 2.5V and
mixed 3.3V input and 2.5V output operating supply modes.
Guaranteed output and part-to-part skew characteristics make
the ICS8344I-01 ideal for those clock distribution applications
demanding well defined performance and repeatability.
FEATURES
Twenty-four LVCMOS/LVTTL outputs,
7Ω typical output impedance
Two selectable differential CLKx, nCLKx inputs
CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the
following input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 200MHz
Translates any single ended input signal to LVCMOS/LVTTL
with resistor bias on nCLK input
Synchronous clock enable
Output skew: 250ps (maximum)
Part-to-part skew: 1ns (maximum)
Bank skew: 125ps (maximum)
Propagation delay: 5.25ns (maximum)
Output supply modes:
Core/Output
3.3V/3.3V
2.5V/2.5V
3.3V/2.5V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK_SEL
CLK0
nCLK0
CLK1
nCLK1
0
1
CLK_EN
LE
Q
nD
Q0:Q7
Q8:Q15
Q16:Q23
Q16
Q17
VDDO
GND
Q18
Q19
Q20
Q21
VDDO
GND
Q22
Q23
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 ICS8344-01 33
5
48-Lead LQFP
32
6 7mm x 7mm x 1.4mm 31
7
8
9
10
package body
Y Package
Top View
30
29
28
27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
Q7
Q6
VDDO
GND
Q5
Q4
Q3
Q2
VDDO
GND
Q1
Q0
OE
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT/ ICSLVCMOS/LVTTL FANOUT BUFFER
1
ICS8344AYI-01 REV. B MAY 10, 2007



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ICS8344I-01 pdf
ICS8344I-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2, 5, 6
7, 8, 11, 12
Q16, Q17, Q18, Q19
Q20, Q21, Q22, Q23
Output
Q16 thru Q23 outputs. 7Ω typical output impedance.
3, 9, 28,
34, 39, 45
4, 10, 14,18,
27, 33, 40, 46
13
www.DataSheet41U5,.c1o9m
16
VDDO
GND
CLK_SEL
VDD
nCLK1
Power
Output supply pins.
Power
Input
Power
Input
Power supply ground.
Clock select input. When HIGH, selects CLK1, nCLK inputs,
Pulldown When LOW, selects CLK0, nCLK0 inputs.
LVCMOS / LVTTL interface levelss.
Core supply pins.
Pullup Inverting differential LVPECL clock input.
17
CLK1
Input Pulldown Non-inverting differential LVPECL clock input.
20
nCLK0
Input Pullup Inverting differential LVPECL clock input.
21
CLK0
Input Pulldown Non-inverting differential LVPECL clock input.
22
CLK_EN
Input
Pullup
Synchronizing control for enabling and disabling clock
outputs. LVCMOS interface levels.
23
OE
Input
Pullup
Output enable. Controls enabling and disabling of outputs
Q0 thru Q23. LVCMOS / LVTTL interface levels.
24
nc Unused
No connect.
25, 26, 29, 30
31, 32, 35, 36
Q0, Q1, Q2, Q3
Q4, Q5, Q6, Q7
Output
Q0 thru Q7 outputs. 7Ω typical output impedance.
37, 38, 41, 42
43, 44, 47, 48
Q8, Q9, Q10, Q11
Q12, Q13, Q14, Q15
Output
Q8 thru Q15 outputs. 7Ω typical output impedance.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C
IN
CPD
RPULLUP
RPULLDOWN
ROUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Test Conditions
Minimum Typical Maximum Units
4 pF
pF
51 KW
51 KΩ
5 7 12 Ω
IDT/ ICSLVCMOS/LVTTL FANOUT BUFFER
2
ICS8344AYI-01 REV. B MAY 10, 2007



Part Number ICS8344I-01
Description 1-TO-24 DIFFERENTIAL -TO-LVCMOS/LVTTL FANOUT BUFFER
Maker Integrated Device Technology - Integrated Device Technology
Total Page 13 Pages
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