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Integrated Device Technology Electronic Components Datasheet



ICS831752I

Clock Switch


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ICS831752I pdf
Clock Switch for ATCA/AMC and
PCIe Applications
ICS831752I
DATA SHEET
General Description
The ICS831752I is a high-performance, differential HCSL clock
switch. The device is designed for the routing of PCIe clock signals in
ATCA/AMC system and is optimized for PCIe Gen 1, Gen 2 and Gen
3. The device has one differential, bi-directional I/O (FCLK) for
connection to ATCA clock sources and to clock receivers through a
connector. The differential clock input CLK is the local clock input and
the HCSL output Q is the local clock output. In the common clock
mode, FCLK serves as an input and is routed to the differential HCSL
output Q. There are two local clock modes. In the local clock mode 0,
CLK is the input, Q is the clock output and FCLK is in high-impedance
state. In the local clock mode 1, CLK is the input and both Q and
FCLK are the outputs of the locally generated PCIe clock signal. The
ICS831752I is characterized to operate from a 3.3V power or 2.5V
power supply. The ICS831752I supports the switching of PCI Express
(2.5 Gb/s), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) clock signals.
Pin Assignment
DIR_SEL
nOEFCLK
VDD
FCLK
nFCLK
GND
CLK
nCLK
1
2
3
4
5
6
7
8
16 IREF
15 GND
14 VDD
13 Q
12 nQ
11 GND
10 VDD
9 nc
ICS831752I
16-lead TSSOP
4.4mm x 5.0mm x 0.925mmpackage body
G Package, Top View
Features
Clock switch for PCIe and ATCA/AMC applications
Supports local and common ATCA/AMC clock modes
Bi-directional clock I/O FCLK:
- When operating as an output, FCLK is a source-terminated
HCSL signal.
- When operating as an input, FCLK accepts HCSL, LVDS and
LVPECL levels.
Local clock input (CLK) accepts HCSL, LVDS and LVPECL
differential signals
Local HCSL clock output (Q)
Maximum input/output clock frequency: 500MHz
Maximum input/output data rate: 1000Mb/s (NRZ)
LVCMOS interface levels for the control inputs
PCI Express (2.5 Gb/S), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) jitter
compliant
Full 3.3V or 2.5V supply voltage
Lead-free (RoHS 6) 16-lead TSSOP package
-40°C to 85°C ambient operating temperature
Block Diagram
FCLK
nFCLK
50 50
22.33
22..33
Pulldown
CLK
Pullup/Pulldown
nCLK
Pullup
nOEFCLK
Pulldown
DIR_SEL
IREF
1=disable
1
Q
nQ
0 50 50
ICS831752AGI REVISION A JUNE 28, 2012
1
©2012 Integrated Device Technology, Inc.



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ICS831752I pdf
ICS831752I Data Sheet
CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS
Table 1. Pin Descriptions
Number
Name
Type
Description
1
DIR_SEL
Input
Pulldown
Direction control for the FCLK I/O. Works in conjunction with nOEFCLK.
See Table 3 for function. LVCMOS/LVTTL interface levels.
2
3, 10, 14
nOEFCLK
VDD
Input
Power
4, 5
FCLK, nFCLK
I/O
6, 11, 15
7
8
9
12, 13
16
GND
CLK
nCLK
nc
nQ, Q
IREF
Power
Input
Input
Unused
Output
Input
Pullup
Pulldown
Pulldown/Pullup
Output enable for the FCLK I/O output. Works in conjunction with
DIR_SEL. See Table 3 for function. LVCMOS/LVTTL interface levels.
Core and output power supply pin.
Differential I/O. Signal direction is controlled by DIR_SEL. Accepts
differential signals when operating as an input. Differential HCSL
signals when operating as an output. Internal source termination can be
disabled. See Table 3 for function.
Power supply ground.
Non-inverting input.
Inverting differential clock input.
No connect.
Differential output pair. HCSL interface levels.
An external fixed precision resistor (475) from this pin to ground
provides a reference current used for the differential current-mode Q
and FCLK outputs.
NOTE: Pullup and pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLDOWN
RPULLUP
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
Function Table
Table 3. Direction Control Function Table
Input
Input
DIR_SEL nOEFCLK Operation
FCLK Function
0
0
Local clock mode 0. The input signal at CLK is routed to Differential HCSL output with internal 50source
both outputs Q and FCLK.
termination
0 (default)
1 (default)
Local clock mode 1. The input signal at CLK is routed to Output is disabled (high impedance). Internal 50
the output Q.
termination is disabled.
1
X
Common reference clock mode. FCLK is the clock input.
Q is the clock output.
Differential clock input. Internal 50source
termination is disabled as well as output driver and
22.33resistors.
NOTE: X = 0 or 1
ICS831752AGI REVISION A JUNE 28, 2012
2
©2012 Integrated Device Technology, Inc.



Part Number ICS831752I
Description Clock Switch
Maker Integrated Device Technology - Integrated Device Technology
Total Page 16 Pages
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