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ICS8308I

1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER


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ICS8308I pdf
LOW SKEW, 1-TO-8 DIFFERENTIAL/
LVCMOS-TO-LVCMOS FANOUT BUFFER
GENERAL DESCRIPTION
The ICS8308I is a low-skew, 1-to-8 Fanout Buffer
and a member of the HiPerClockS™family of High
Perfor mance Clock Solutions from IDT. The
ICS8308I has two selectable clock inputs. The CLK,
nCLK pair can accept most differential input levels.
The LVCMOS_CLK can accept LVCMOS or LVTTL input levels.
The low impedance LVCMOS/LVTTL outputs are designed to
drive 50Ω series or parallel terminated transmission lines. The
www.DataeSfhfeeectt4ivUe.cfoamnout can be increased from 8 to 16 by utilizing the
ability of the outputs to drive two series terminated trans-
mission lines.
The ICS8308I is characterized for 3.3V core/3.3V output,
3.3V core/2.5V output or 2.5V core/2.5V output operation.
Guaranteed output and part-part skew characteristics make
the 8308I ideal for those clock distribution applications requiring
well defined performance and repeatability.
ICS8308I
FEATURES
Eight LVCMOS/LVTTL outputs, (7Ω typical output impedance)
Selectable LVCMOS_CLK or differential CLK, nCLK inputs
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum Output Frequency: 350MHz
Output Skew: (3.3V± 5%): 100ps (maximum)
Part to Part Skew: (3.3V± 5%): 1ns (maximum)
Supply Voltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
CLK_EN Pullup
LVCMOS_CLK Pullup
CLK Pullup
nCLK Pulldown
CLK_SEL Pullup
1
0
D
Q
LE
OE Pullup
IDT/ ICSLVCMOS FANOUT BUFFER
PIN ASSIGNMENT
Q0 1
GND 2
24 VDDO
23 Q2
CLK_SEL 3
22 GND
LVCMOS_CLK 4
21 Q3
Q0
CLK 5
20 VDDO
nCLK 6
19 Q4
Q1
CLK_EN 7
18 GND
OE 8
17 Q5
Q2
VDD 9
16 VDDO
GND 10 15 Q6
Q3 Q1 11 14 GND
VDDO 12
13 Q7
Q4
ICS8308I
Q5 24-Lead, 173-MIL TSSOP
Q6 4.4mm x 7.8mm x 0.925mm body package
G Package
Q7 Top View
1 ICS8308AGI REV. B OCTOBER 16, 2007



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ICS8308I pdf
ICS8308I
LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 11, 13, 15,
17, 19, 21, 23
Q0, Q1, Q7, Q6,
Q5, Q4,Q3, Q2
Output
Clock outputs. LVCMOS / LVTTL interface levels.
2, 10, 14, 18, 22
GND
Power
Power supply ground.
Clock select input. Selects LVCMOS clock input when HIGH.
3
CLK_SEL
Input Pullup Selects CLK, nCLK inputs when LOW. See Table 3A.
LVCMOS / LVTTL interface levels.
4 LVCMOS_CLK Input Pullup Clock input. LVCMOS / LVTTL interface levels.
5 CLK Input Pullup Non-inverting differential clock input.
6
www.DataSheet4U.co7m
nCLK
CLK_EN
Input Pulldown Inverting differential clock input.
Input Pullup Clock enable. LVCMOS / LVTTL interface levels.
8
OE
Input
Pullup
Output enable. LVCMOS / LVTTL interface levels.
See Table 3B.
9
VDD Power
Core supply pin.
12, 16, 20, 24
VDDO
Power
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
CPD
RPULLUP
RPULLDOWN
ROUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Test Conditions
Minimum
5
Typical
4
12
51
51
7
Maximum
12
Units
pF
pF
kΩ
kΩ
Ω
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input
CLK_SEL
0
1
Clock Input
CLK, nCLK is selected
LVCMOS_CLK is selected
TABLE 3B. OE SELECT FUNCTION TABLE
Control Input
OE
0
1
Output Operation
Outputs Q0:Q7 are in Hi-Z (disabled)
Outputs Q0:Q7 are active (enabled)
TABLE 3C. CLOCK INPUT FUNCTION TABLE
Inputs
CLK_SEL LVCMOS_CLK
CLK
nCLK
Outputs
Q0:Q7
Input to Output Mode
Polarity
0—
0
1 LOW Differential to Single Ended Non Inverting
0—
1
0 HIGH Differential to Single Ended Non Inverting
0—
0 Biased; NOTE 1 LOW Single Ended to Single Ended Non Inverting
0—
1 Biased; NOTE 1 HIGH Single Ended to Single Ended Non Inverting
0
— Biased; NOTE 1
0
HIGH Single Ended to Single Ended Inverting
0
— Biased; NOTE 1
1
LOW Single Ended to Single Ended Inverting
1 0 — — LOW Single Ended to Single Ended Non Inverting
1 1 — — HIGH Single Ended to Single Ended Non Inverting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
IDT/ ICSLVCMOS FANOUT BUFFER
2 ICS8308AGI REV. B OCTOBER 16, 2007



Part Number ICS8308I
Description 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Maker Integrated Device Technology - Integrated Device Technology
Total Page 16 Pages
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