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ICS8305I

MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER



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ICS8305I pdf
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS8305I is a low skew, 1-to-4, Differential/LVCMOS-to-
LVCMOS/LVTTL Fanout Buffer. The ICS8305I has selectable
clock inputs that accept either differential or single ended
input levels. The clock enable is internally synchronized to
eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin. Outputs are
forced LOW when the clock is disabled. A separate output
enable pin controls whether the outputs are in the active or
high impedance state.
Guaranteed output and part-to-part skew characteristics make
the ICS8305I ideal for those applications demanding well de-
fined performance and repeatability.
FEATURES
• 4 LVCMOS/LVTTL outputs
• Selectable differential or LVCMOS/LVTTL clock inputs
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• LVCMOS_CLK supports the following input types:
LVCMOS, LVTTL
• Maximum output frequency: 350MHz
• Output skew: 40ps (maximum)
• Part-to-part skew: 700ps (maximum)
Additive phase jitter, RMS: 0.04ps (typical)
• 3.3V core, 3.3V, 2.5V or 1.8V output operating supply
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
CLK_EN
LVCMOS_CLK
CLK
nCLK
CLK_SEL
00
11
D
Q
LE
OE
PIN ASSIGNMENT
GND 1 16 Q0
OE 2
1 5 VDDO
VDD 3
14 Q1
CLK_EN 4 13 GND
CLK 5 12 Q2
Q0
nCLK 6
1 1 VDDO
CLK_SEL 7 10 Q3
Q1
LVCMOS_CLK 8
9 GND
Q2 ICS8305I
16-Lead TSSOP
4.4mm x 3.0mm x 0.92mm package body
Q3 G Package
Top View
8305AGI
www.idt.com
1
REV. B SEPTEMBER 17, 2012



No Preview Available !

ICS8305I pdf
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 9, 13
GND
Power
Power supply ground.
2
OE
Input
Pullup
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
3
VDD Power
Core supply pin.
Synchronizing clock enable. When LOW, the output clocks are
4
CLK_EN
Input Pullup disabled. When HIGH, output clocks are enabled.
LVCMOS / LVTTL interface levels.
5
CLK
Input Pulldown Non-inverting differential clock input.
6
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. VDD/2 default when left floating.
Clock select input. When HIGH, selects CLK, nCLK inputs.
7
CLK_SEL
Input Pullup When LOW, selects LVCMOS_CLK input.
LVCMOS / LVTTL interface levels.
8 LVCMOS_CLK Input Pulldown LVCMOS / LVTTL clock input.
10, 12, 14, 16 Q3, Q2, Q1, Q0 Output
Clock outputs. LVCMOS / LVTTL interface levels.
11, 15
VDDO
Power
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C
IN
RPULLUP
RPULLDOWN
CPD
ROUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
11 pF
5 7 12 Ω
8305AGI
www.idt.com
2
REV. B SEPTEMBER 17, 2012



Part Number ICS8305I
Description MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Maker Integrated Device Technology - Integrated Device Technology
Total Page 16 Pages
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