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Integrated Device Technology Electronic Components Datasheet



ICS83023I

1-TO-1 DIFFERENTIAL-TOLVCMOS TRANSLATOR/BUFFER



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ICS83023I pdf
DATA SHEET
DUAL, 1-TO-1ICnDitrecIguFriatFtedERENTIAL-TO-
LVCMOS TRASNysSteLmsA, ITncO. R/BUFFER
ICS83I0C2S38I3023I
DUAL, 1-TO-1
DIFFERENTIAL-TO-LVCMOS TRANSLATOR /BUFFER
GENERAL DESCRIPTION
The ICS83023I is a dual, 1-to-1 Differential-to-
ICS LVCMOS Translator/Fanout Buffer and a mem-
HiPerClockS™ ber of the HiPerClockS™ family of High Perfor-
mance Clock Solutions from ICS. The differen-
tial inputs can accept most differential signal
www.DataSheet4U.ctoympes (LVDS, LVHSTL, LVPECL, SSTL, and HCSL) and
translate into two single-ended LVCMOS outputs. The small
8-lead SOIC footprint makes this device ideal for use in ap-
plications with limited board space.
Features
Two LVCMOS / LVTTL outputs
Two differential CLKx, nCLKx input pairs
CLK, nCLK pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 350MHz (typical)
Output skew: 60ps (maximum)
Part-to-part skew: 500ps (maximum)
Additive phase jitter, RMS: 0.14ps (typical)
Small 8 lead SOIC package saves board space
3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
CLK0
nCLK0
CLK1
nCLK1
Q0
Q1
PIN ASSIGNMENT
CLK0
nCLK0
nCLK1
CLK1
1
2
3
4
8 VDD
7 Q0
6 Q1
5 GND
ICS83023I
8-Lead SOIC
3.8mm x 4.8mm x 1.47mm package body
M Package
Top View
83023AMI
www.icst.com/products/hiperclocks.html
IDT™ / ICS™ DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
1
1
REV. B JANUARY 18, 2006
ICS83023I



No Preview Available !

ICS83023I pdf
ICS83023IICS83023I
Integrated
Circuit
D , 1- -1DUAL, 1-TO-1 DIFSFyEsRtEemNTsI,AILn-cT.O-LVCMOS TRANSLATOR/BUFFER
D - -LVCMOS T /BIFFERENTIAL TO
UAL TO TSD
RANSLATOR UFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
CLK0
Input Pulldown Non-inverting differential clock input.
2
nCLK0
Input
Pullup Inverting differential clock input.
3
nCLK1
Input
Pullup Inverting differential clock input.
4
CLK1
Input Pulldown Non-inverting differential clock input.
5
GND
Power
Power supply ground.
6 Q1 Output
Single clock output. LVCMOS / LVTTL interface levels.
7 Q0 Output
Single clock output. LVCMOS / LVTTL interface levels.
www.DataSheet4U.co8m
VDD Power
Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
CPD
RPULLUP
RPULLDOWN
ROUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Test Conditions
VDD = 3.6V
Minimum
Typical
4
23
51
51
7
Maximum Units
pF
pF
kΩ
kΩ
Ω
83023AMI
www.icst.com/products/hiperclocks.html
2
IDT™ / ICS™ DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
2
REV. B JANUARY 18, 2006
ICS83023I



Part Number ICS83023I
Description 1-TO-1 DIFFERENTIAL-TOLVCMOS TRANSLATOR/BUFFER
Maker Integrated Device Technology - Integrated Device Technology
Total Page 13 Pages
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