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Integrated Device Technology Electronic Components Datasheet



ICS551

1 TO 4 CLOCK BUFFER


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ICS551 pdf
1 TO 4 CLOCK BUFFER
DATASHEET
ICS551
Description
The ICS551 is a low cost, high-speed single input to
four output clock buffer. Part of IDT’s ClockBlocksTM
family, this is our lowest cost, small clock buffer.
See the ICS552-02B for monolithic dual version of the
ICS551 in a 20 pin QSOP.
IDT makes many non-PLL and PLL based low skew
output devices as well as Zero Delay Buffers to
synchronize clocks. Contact IDT for all of your clocking
needs.
Features
Low skew (250 ps) outputs
Pb-free packaging
Low cost clock buffer
Packaged in 8-pin SOIC
Input/Output clock frequency up to 160 MHz
Non-inverting output clock
Ideal for networking clocks
Operating Voltages of 3.3 and 5.0 V
Output Enable mode tri-states outputs
Advanced, low power CMOS process
Commercial and industrial temperature versions
Block Diagram
ICLK
Q1
Q2
Q3
Q4
Output Enable
IDT™ 1 TO 4 CLOCK BUFFER
1
ICS551
REV P 051310



No Preview Available !

ICS551 pdf
ICS551
1 TO 4 CLOCK BUFFER
Pin Assignment
ICLK
Q1
Q2
Q3
1
2
3
4
8 OE
7 VDD
6 GND
5 Q4
8 Pin (150 mil) SOIC
FAN OUT BUFFER
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
ICLK
Q1
Q2
Q3
Q4
GND
VDD
OE
Pin
Type
Pin Description
Input Clock input. Internal pull-up resistor.
Output Clock output 1.
Output Clock output 2.
Output Clock output 3.
Output Clock output 4.
Power Connect to ground.
Power Connect to 3.3 V or 5.0 V.
Input Output Enable. Tri-states outputs when low. Internal pull-up resistor.
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of
0.01 µF should be connected between VDD on pin 7 and GND on pin 6, as close to the device as possible.
A 33series terminating resistor may be used on each clock output if the trace is longer than 1 inch.
IDT™ 1 TO 4 CLOCK BUFFER
2
ICS551
REV P 051310



Part Number ICS551
Description 1 TO 4 CLOCK BUFFER
Maker IDT - IDT
Total Page 9 Pages
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