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GlobespanVirata
GlobespanVirata


G2237-208-041PTC1

Transceiver



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G2237-208-041PTC1 pdf
June 25, 2002, Issue 2
Part Numbers
G2216-208-041PF B2 (SDSL 2B1Q)
G2214-208-041DF B2 (SDSL CAP)
G2237-208-041PT B2 (SHDSL/HDSL2)
G2237-208-041PT C1 (SHDSL/HDSL2)
XDSL2TM SDSL, HDSL2, or SHDSL - ILD2
Dual-Channel, Low Power, Programmable
Transceiver with Integrated Framer and Line Drivers
Data Sheet
Overview
The GlobespanVirata® XDSL2™ Digital Subscriber Line
(DSL) chip sets provide low power, high density solutions for
2-wire DSL equipment. These chip sets are fully
programmable and field upgradeable eliminating the risk of
product obsolescence and accelerating the time-to-market for
new network services. The GlobespanVirata® XDSL2™ DSL
chip sets are fully interoperable with multi-vendor DSL chip
set solutions. This interoperability enables dynamic
interworking of multiple vendor DSL solutions with the
capability to interoperate with products that conform to ANSI
and ETSI DSL standards.
GlobespanVirata’s unique hardware platform supports
multiple dual-channel applications including SDSL, HDSL2,
and SHDSL, using population options for optimization.
The XDSL2 DSL chip sets incorporate two DSL bit pumps
plus framing into a three-chip solution comprised of a dual-
channel digital signal processor (DSP) with built-in framer and
two Analog Front Ends each with an Integrated Line Driver
(ILD2).
The XDSL2 chip sets interface directly with off-the-shelf T1/
E1 transceivers and Nx64 multiplexing, eliminating the need
for a separate DSL framer to combine and format the two DSL
channels into a standard interface. GlobespanVirata’s DSL
XDSL2 chip sets deliver two channels of full duplex
transmission up to 2320 kb/s, depending on the application.
The high density XDSL2 dual-channel DSL chip sets are ideal
for CO applications, while single-channel versions with
integrated framer are also available for CPE applications.
Features
Dual-channel DSP with framer that fully integrates
2 separate DSL chips into a single device
Two AFEs, each with an integrated differential line driver
2B1Q, CAP, or PAM line codes
Supports dual-channel symmetric data rates of 144 kb/s
to 2320 kb/s (depending on the application)
Supports IDSL with optional data interface rates of
64 kb/s, 128 kb/s, and 144 kb/s
Offers physical layer interoperability with competitive solu-
tions
Glueless interface to popular microprocessors
Transmission compliant with ETSI TS 101 135, ITU-T
G.991.1, and ANSI TR-28 for single pair 2B1Q and CAP,
ANSI T1.418 for HDSL2 and ITU-T G.991.2 for SHDSL
Reference design compatible with Bellcore GR-1089, IEC
60950, UL 1950, ITU-T K.20 and K.21
Built-in framer provides easy access to EOC and indicator
bits (framing can be bypassed completely for 2-channel
independent operation)
Interfaces directly with off-the-shelf single-channel T1/E1
transceivers
ATM UTOPIA Level 1 and 2 interface
A single oscillator and hybrid topology supports all speeds
+3.3V and +5V power supplies
Customer Interface
TDATA (A/B)
TClock (A/B)
Frame Pulse (A/B)
RDATA (A/B)
Rclock (A/B)
Frame Pulse (A/B)
Dual
Channel
DSP
w/Framer
µ Processor Interface
ILD2
ILD2
Figure 1. Block Diagram of XDSL2™ DSP with Two Single-Channel ILD2s
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions
DO-009643-DS, Issue 2



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G2237-208-041PTC1 pdf
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
June 25, 2002
Introduction
The GlobespanVirata DSL chip sets support
applications ranging from remote network access,
digital pair gain, video conferencing, and cellular base
station land-line connectivity, for T1/E1 services. Up to
36 voice circuits may be provisioned over a single
copper pair.
Example Applications
Compatibility with voice/data pair gain systems
Cellular and microcellular systems
T1/E1 and fractional T1/E1 DSL transceiver
Wireless base station connectivity
Related Materials
To accelerate time-to-market, GlobespanVirata offers
our customers a comprehensive Design Guide which
includes details on planning, layout, testing, debugging,
and expert tips and recommendations for building a
successful DSL product. The Design Guide is
distributed as part of a Design Package which includes
firmware, transceiver schematics, sample code,
transceiver layout Gerber files, and Bill of Materials.
For rapid prototyping, Quick Kits are available. These
Quick Kits contain all transceiver design BOM
components in kit form so there’s no component lead
time delay.
The Super GlobespanVirata Development System
(SGDSTM), an easy-to-use evaluation and development
platform designed to support all GlobespanVirata xDSL
transceiver solutions, is also available for early product
development.
The SGDS also provides an interface to the
GlobespanVirata Microsoft® Windows® - based Host
Interface Program (WHIP). When the SGDS is teamed
with WHIP, product evaluation, testing and debugging is
achieved with the click of a mouse.
GlobespanVirata Transceiver System
Overview
The GlobespanVirata XDSL2™ DSL chip sets con-
sist of a dual-channel DSP with an on-chip framer,
and two single-channel AFEs (with ILD2).
The single-channel ILD2s filter and digitize the sig-
nal received on the telephone line and for the trans-
mit side, generate analog signals from the digital
data and filter the analog signals to create the
2B1Q, CAP or PAM transmit signal (depending on
the line code).
The GlobespanVirata Windows-based Host Inter-
face Program (WHIP) is offered as part of the
GlobespanVirata transceiver system development
package for SDSL 2B1Q, HDSL2, and SHDSL
applications. WHIP allows you to test and debug
your product design with the click of a mouse. This
graphical interface allows you to send commands,
perform trace and debug procedures, and initiate a
startup on both the CO and CP units. WHIP offers
complete flexibility and modularity - you can rear-
range windows and toolbars to suit your prefer-
ences and design requirements.
SDSL CAP applications are offered the Globespan-
Virata Host Interface Program (HIP) software as
part of the GlobespanVirata transceiver system
development package. The PC-based HIP software
provides a PC interface to the host. HIP allows the
host to run scripts to obtain and manipulate data,
test performance, and debug the software. No addi-
tional software or special PC hardware or tools are
required. Customers who use HIP with their host
processor receive the benefits of faster diagnosis
and specialized assistance from the GlobespanVi-
rata staff.
GlobespanVirata, Inc. — Proprietary
2
Use pursuant to Company Instructions
DO-009643-DS, Issue 2



Part Number G2237-208-041PTC1
Description Transceiver
Maker GlobespanVirata - GlobespanVirata
Total Page 30 Pages
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