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Cypress Semiconductor Electronic Components Datasheet



CY2302

Frequency Multiplier and Zero Delay Buffer


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Features
90 ps typical jitter OUT2
200 ps typical jitter OUT1
65 ps typical output-to-output skew
90 ps typical propagation delay
Voltage range: 3.3 V±5%, or 5 V±10%
Output frequency range: 5 MHz to 133 MHz
Two outputs
Configuration options allow various multiplications of the
reference frequency—refer to Table 1 to determine the
specific option which meets your multiplication needs
Available in 8-pin SOIC package
CY2302
Frequency Multiplier and
Zero Delay Buffer
Table 1. Configuration Options
FBIN
OUT1
OUT1
OUT1
OUT1
OUT2
OUT2
OUT2
OUT2
FS0 FS1
OUT1
0 0 2 X REF
1 0 4 X REF
01
REF
1 1 8 X REF
0 0 4 X REF
1 0 8 X REF
0 1 2 X REF
1 1 16 X REF
OUT2
REF
2 X REF
REF/2
4 X REF
2 X REF
4 X REF
REF
8 X REF
Logic Block Diagram
FBIN
External feedback connection to
OUT1 or OUT2, not both
FS0
FS1 ÷Q
IN
Reference
Input
Phase
Detector
Charge
Pump
Loop
Filter
Output
Buffer
VCO
÷2
Output
Buffer
OUT1
OUT2
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-07154 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 24, 2011
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CY2302
Pinouts
Figure 1. Pin Configuration – 8-Pin SOIC Package
FBIN
IN
GND
FS0
1
2
3
4
8 OUT2
7 VDD
6 OUT1
5 FS1
Table 2. Pin Definition
Pin Name Pin No
IN
FBIN
2
1
OUT1
OUT2
VDD
GND
FS0:1
6
8
7
3
4, 5
Pin
Type
I
I
O
O
P
P
I
Pin Description
Reference Input: The output signals are synchronized to this signal.
Feedback Input: This input must be fed by one of the outputs (OUT1 or OUT2) to ensure
proper functionality. If the trace between FBIN and the output pin being used for feedback is
equal in length to the traces between the outputs and the signal destinations, then the signals
received at the destinations are synchronized to the REF signal input (IN).
Output 1: The frequency of the signal provided by this pin is determined by the feedback
signal connected to FBIN, and the FS0:1 inputs (see Table 1).
Output 2: The frequency of the signal provided by this pin is one-half of the frequency of
OUT1. See Table 1.
Power Connections: Connect to 3.3V or 5V. This pin should be bypassed with a 0.1-F
decoupling capacitor. Use ferrite beads to help reduce noise for optimal jitter performance.
Ground Connection: Connect all grounds to the common system ground plane.
Function Select Inputs: Tie to VDD (HIGH, 1) or GND (LOW, 0) as desired per Table 1.
Document #: 38-07154 Rev. *E
Page 2 of 9
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Part Number CY2302
Description Frequency Multiplier and Zero Delay Buffer
Maker Cypress Semiconductor - Cypress Semiconductor
Total Page 9 Pages
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