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Cypress Semiconductor Electronic Components Datasheet



CY22801

Universal Programmable Clock Generator


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Features
• Integrated phase-locked loop (PLL)
• Field programmable
• Input frequency range:
— Crystal: 8–30 MHz
— CLKIN: 1–133 MHz
• Output frequency:
— LVCMOS: 1–200 MHz
• Low jitter, high accuracy outputs
• 3.3V operation
• 8-pin SOIC package
Logic Block Diagram
XIN/CLKIN
XOUT
XTAL
OSC
PLL
CY22801
Universal Programmable Clock
Generator (UPCG)
Benefits
• Inventory of only one device, CY22801, is needed to use in
various applications
• In-house programming of samples and prototype quantities
is available using the CY36800 InstaClock Kit
• Can customize the input and output frequencies to suit your
needs
• High-performance PLL tailored for multiple applications
• Meets critical timing requirements in complex system
designs
• Enables application compatibility
OUTPUT
DIVIDERS
CLKA
CLKB
CLKC
Pin Configuration
CY22801
8-pin SOIC
XIN/CLKIN
VDD
NC
VSS
1
2
3
4
8 XOUT
7 CLKC
6 CLKA
5 CLKB
Pin Description
Name
XIN
VDD
NC
VSS
CLKB
CLKA
CLKC
XOUT
Pin Number Description
1 Reference Input: Crystal or External Clock
2 3.3V Voltage Supply
3 No Connect; leave this pin floating
4 Ground
5 Clock Output B
6 Clock Output A
7 Clock Output C
8 Reference Output: Connect to external crystal. When the reference is an external clock
signal, this pin is not used and must be left floating.
Cypress Semiconductor Corporation
Document #: 001-15571 Rev. **
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised May 10, 2007
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CY22801 pdf
CY22801
General Description
The CY22801 is a flash-programmable clock generator that
supports various applications in consumer and communica-
tions markets. The device uses a Cypress proprietary PLL to
drive up to three configurable outputs in an 8-pin SOIC.
The CY22801 can be programmed with an easy-to-use
programmer dongle, the CY36800, in conjunction with the
CyClocksRT™ software. This enables fast sample generation
of prototype builds for user-defined frequencies.
Field Programming the CY22801
The CY22801 is programmed using the CY36800 USB
programmer dongle. The CY22801 is flash-technology based,
so the parts can be reprogrammed up to 100 times. This
enables fast and easy design changes and product updates,
and eliminates any issues with old and out-of-date inventory.
Samples and small prototype quantities can be programmed
using the CY36800 programmer. Cypress’s value added distri-
bution partners and third party programming systems from BP
Microsystems, HiLo Systems, and others, are available for
large production quantities.
CyClocksRT Software
CyClocksRT is an easy-to-use software application that
enables the user to custom-configure the CY22801. Users can
specify the XIN/CLKIN frequency, crystal load capacitance,
and output frequencies. CyClocksRT then creates an
industry-standard JEDEC file, which is used to program the
CY22801.
When needed, an advanced mode is available that enables
users to override the automatically generated VCO frequency
and output divider values.
CyClocksRT is a component of the CyberClocks™ software,
which can be downloaded free of charge from the Cypress
website at http://www.cypress.com.
CY36800 InstaClock™ Kit
The Cypress CY36800 InstaClock Kit comes with everything
needed to design the CY22801 and program samples and
small prototype quantities. The CyClocksRT software is used
to quickly create a JEDEC programming file, which is then
downloaded directly to the portable programmer that is
included in the CY36800 InstaClock Kit. The JEDEC file can
also be saved for use in a production programming system for
larger volumes.
The CY36800 also comes with five samples of the CY22800,
which can be programmed with preconfigured JEDEC files
using the InstaClock software.
Output Clock Frequencies
The CY22801 is a very flexible clock generator with up to three
individual outputs, generated from an integrated PLL. Details
are shown in Figure 1.
The output of the PLL runs at high frequency and is divided
down to generate the output clocks. Two programmable
dividers are available for this purpose. Thus, although the
output clocks may be different frequencies, they must be
related, based on the PLL frequency.
It is also possible to direct the reference clock input to any of
the outputs, thereby bypassing the PLL. Lastly, the reference
clock may be passed through either divider.
Figure 1. Basic PLL Block Diagram
REF
(XIN/CLKIN)
/Q PFD
VCO
/P
Post
Divider
1N
Post
Divider
2N
Crosspoint
Switch
Matrix
CLKA
CLKB
CLKC
Reference Crystal Input
The input crystal oscillator of the CY22801 is an important
feature because of the flexibility it allows the user in selecting
a crystal as a reference clock source. The oscillator inverter
has programmable gain, enabling maximum compatibility with
a reference crystal, based on manufacturer, process, perfor-
mance, and quality.
Input load capacitors are placed on the CY22801 die to reduce
external component cost. These capacitors are true
parallel-plate capacitors, designed to reduce the frequency
shift that occurs when nonlinear load capacitance is affected
by load, bias, supply, and temperature changes.
The value of the input load capacitors is determined by eight
bits in a programmable register. Total load capacitance is
determined by the formula:
CapLoad = (CL – CBRD – CCHIP)/0.09375 pF
In CyClocksRT, enter the crystal capacitance (CL). The value
of CapLoad will be determined automatically and programmed
into the CY22801.
Applications
Controlling Jitter
Jitter is defined in many ways, including:
• Phase noise
• Long-term jitter
• Cycle-to-cycle jitter
• Period jitter
• Absolute jitter
• Deterministic jitter
Document #: 001-15571 Rev. **
Page 2 of 7
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Part Number CY22801
Description Universal Programmable Clock Generator
Maker Cypress Semiconductor - Cypress Semiconductor
Total Page 7 Pages
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