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Cypress Semiconductor Electronic Components Datasheet



CY2277A

K6 Clock Synthesizer/Driver


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CY2277A
Pentium®/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/
Mobile PCs with Intel® 82430TX and 2 DIMMs or 3 SO-DIMMs
Features
• Mixed 2.5V and 3.3V operation
• Complete clock solution to meet requirements of Pen-
tium®, Pentium® II, 6x86, or K6 motherboards
Four CPU clocks at 2.5V or 3.3V
Up to eight 3.3V SDRAM clocks
Seven 3.3V synchronous PCI clocks, one free
running
Two 3.3V USB/IO clocks at 48 or 24 MHz, selectable
by serial interface
One 2.5V IOAPIC clock at 14.318 MHz
Two 3.3V Ref. clocks at 14.318 MHz
Factory-EPROM programmable CPU, PCI, and USB/IO
clock frequencies for custom configuration
Factory-EPROM programmable output drive and slew
rate for EMI customization
MODE Enable pin for CPU_STOP and PCI_STOP
SMBus serial configuration interface
Available in space-saving 48-pin SSOP and TSSOP
packages.
Functional Description
The CY2277A is a Clock Synthesizer/Driver for Pentium, Pen-
tium II, 6X86, and K6 portable PCs designed with the Intel®
82430TX or similar chipsets. There are three available options
as shown in the selector guide
The CY2277A has power-down, CPU stop and PCI stop pins
for power management control. The CPU stop and PCI stop
are controlled by the MODE pin. They are multiplexed with
SDRAM clock outputs, and are selected when the MODE pin
is driven LOW. Additionally, these inputs are synchronized
on-chip, enabling glitch-free transitions. When the
CPU_STOP input is asserted, the CPU outputs are driven
LOW. When the PCI_STOP input is asserted, the PCI outputs
(except the free-running PCI clock) are driven LOW. Finally,
when the PWR_DWN pin is asserted, the reference oscillator
and PLLs are shut down, and all outputs are driven LOW.
The CY2277A outputs are designed for low EMI emission.
Controlled rise and fall times, unique output driver circuits and
factory-EPROM programmable output drive and slew-rate en-
able optimal configurations for EMI control.
CY2277A Selector Guide
Clock Outputs
-1/-1M -3
-12/
-12M/
-7M -12I
CPU (60, 66.6 MHz) 4 -- 4 4
CPU (33.3, 66.6 MHz) -- 4 -- --
CPU (SMBus select-
--
--
--
--
able)
PCI (CPU/2)
7[1] 7[1] 7[1] 7[1]
SDRAM
6/8 6/8 6/8 6/8
The CY2277A outputs four CPU clocks at 2.5V or 3.3V with up
to nine selectable frequencies. There are up to eight 3.3V
SDRAM clocks and seven PCI clocks, running at one half the
CPU clock frequency. One of the PCI clocks is free-running.
Additionally, the part outputs two 3.3V USB/IO clocks at 48
MHz or 24 MHz, one 2.5V IOAPIC clock at 14.318 MHz, and
two 3.3V reference clocks at 14.318 MHz. The CPU, PCI,
USB, and IO clock frequencies are factory-EPROM program-
mable for easy customization with fast turnaround times.
USB/IO (48 or 24 MHz) 2
IOAPIC (14.318 MHz) 1
Ref (14.318 MHz)
2
CPU-PCI delay
16 ns
Note:
1. One free-running PCI clock.
2
1
2
16 ns
2
1
2
<1 ns
2
1
2
14 ns
Logic Block Diagram
XTALIN
XTALOUT
14.318
MHz
OSC.
CPU
PLL
STOP
LOGIC
SEL
MODE
PWR_DWN
SCLK
SDATA
EPROM
SYS
PLL
SERIAL
INTERFACE
CONTROL
LOGIC
/2
Delay
STOP
LOGIC
Divide and
Mux Logic
Pin Configuration
IOAPIC (14.318 MHz)
VDDQ2
REF [01]
(14.318)
CPUCLK[03]
REF1
REF0
VSS
XTALIN
XTALOUT
SSOP
Top View
1 48
2 47
3 46
4 45
5 44
AVDD
PWR_SEL
VDDQ2
IOAPIC
PWR_DWN
VDDCPU
SDRAM[05]
MODE
VDDQ3
PCICLK_F
PCICLK0
VSS
6
7
8
9
10
43 VSS
42 CPUCLK0
41 CPUCLK1
40 VDDCPU
39 CPUCLK2
SDRAM6/CPU_STOP
PCICLK1
PCICLK2
PCICLK3
11
12
13
38 CPUCLK3
37 VSS
36 SDRAM0
SDRAM7/PCI_STOP
PCICLK4
VDDQ3
PCICLK5
14
15
16
35 SDRAM1
34 VDDQ3
33 SDRAM2
VSS 17
32 SDRAM3
PCI[05]
PCICLK_F
SEL
SDATA
SCLK
18
19
20
31 VSS
30 SDRAM4
29 SDRAM5
VDDQ3
USBCLK/IOCLK[0:1] USBCLK/IOCLK
USBCLK/IOCLK
21
22
23
28 VDDQ3
27 SDRAM6/CPU_STOP
26 SDRAM7/PCI_STOP
VSS 24
25 AVDD
Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600
Document #: 38-07332 Rev. *A
Revised December 7, 2002



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CY2277A
Pin Summary
Name
Pins
Description
VDDQ3
VDDQ2
VDDCPU
AVDD
VSS
XTALIN[2]
XTALOUT[2]
7, 15, 21, 28, 34
3.3V Digital voltage supply
46 IOAPIC Digital voltage supply, 2.5V
40 CPU Digital voltage supply, 2.5V or 3.3V
25, 48
3.3V Analog voltage supply
3, 10, 17, 24, 31, 37, 43 Ground
4 Reference crystal input
5 Reference crystal feedback
MODE
6
Mode select input, enables power management features
SEL 18
Select input to enable 66.66 MHz or 60 MHz CPU clock (See Function
tables.)
SDATA
19
SMBus serial data input for serial configuration port
SCLK
20
SMBus serial clock input for serial configuration port
PWR_DWN
44
Active low control input to put osc., PLLs, and outputs in power down state
PWR_SEL
47
SDRAM7/PCI_STOP 26
Power select input, indicates whether VDDCPU is at 2.5V or 3.3V
HIGH = 3.3V, LOW=2.5V (internal pull-up to VDD)
SDRAM clock output. Also, active LOW control input to stop PCI clocks,
enabled when MODE is LOW
SDRAM6/CPU_STOP 27
SDRAM clock output. Also, active LOW control input to stop CPU clocks,
enabled when MODE is LOW
SDRAM[0:5]
36, 35, 33, 32, 30, 29 SDRAM clock outputs, have same frequency as CPU clocks
CPUCLK[0:3]
42, 41, 39, 38
CPU clock outputs
PCICLK[0:5]
9, 11, 12, 13, 14, 16
PCI clock outputs
PCICLK_F
8
PCI clock output, free-running
IOAPIC
45
IOAPIC clock output
REF[0:1]
1, 2
Reference clock outputs, 14.318 MHz. REF0 drives 45 pF load
USBCLK/IOCLK
22, 23
USB or IO clock outputs, frequency selected by serial word
Note:
2. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF.
Document #: 38-07332 Rev. *A
Page 2 of 19



Part Number CY2277A
Description K6 Clock Synthesizer/Driver
Maker Cypress Semiconductor - Cypress Semiconductor
Total Page 19 Pages
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