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Cypress Semiconductor Electronic Components Datasheet



CY2210

133-MHz Spread Spectrum Clock Synthesizer/Driver with AGP/ USB/ and DRCG Support


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CY2210
133-MHz Spread Spectrum Clock Synthesizer/Driver
with AGP, USB, and DRCG Support
Features
• Mixed 2.5V and 3.3V Operation
• Compliant to Intel® CK133 (CY2210-3) & CK133W
(CY2210-2) synthesizer and driver specification
Multiple output clocks at different frequencies
Four CPU clocks, up to 133 MHz
Eight synchronous PCI clocks, 1 free-running
Two CPU/2 clocks, at one-half the CPU frequency
Four AGP clocks at 66 MHz
Three synchronous APIC clocks, at 16.67 MHz
One USB clock at 48 MHz
Two reference clocks at 14.318 MHz
Spread Spectrum clocking
32.5-kHz modulation frequency @ 133 MHz
33.1-kHz modulation frequency @ 100 MHz for
CY2210-02/03
33.4-kHz modulation frequency @ 100 MHz for
CY2210-04
EPROM programmable percentage of spreading.
Default is 0.6%, which is recommended by Intel
Power-down features
Three Select inputs
Low-skew and low-jitter outputs
OE and Test Mode support
56-pin SSOP package
Benefits
Usable with Pentium® II and Pentium® III processors
Single-chip main motherboard clock generator
Driven together, support 4 CPUs and a chipset
Support for 4 PCI slots and chipset
Drives up to two main memory clock generators, includ-
ing DRCG (CPUCLK/2)
Support for multiple AGP slots
Support multiprocessing systems
Supports USB frequencies and I/O chip
Enables reduction of EMI in some systems
Supports mobile systems
Supports up to eight CPU clock frequencies
Meets tight system timing requirements at high frequency
Enables ATE and bed of nailstesting
Widely available, standard package enables lower cost
Logic Block Diagram
CPU_STOP
XTALIN
XTALOUT
14.318
MHz
OSC.
SEL1
SEL0
SEL133
SPREAD
PCI_STOP
PWR_DWN
CPU
PLL
EPROM
SYS
PLL
Divider,
EPROM-
ProgDelay
and
Stop Logic
Intel and Pentium are registered trademarks of Intel Corporation.
Pin Configuration
SSOP
Top View
REFCLK [01] (14.318 MHz) VSSREF
REFCLK0
REFCLK1
CPUCLK [03]
VDDREF
XTALIN
CPUCLK/2 [01] (DRCG)
XTALOUT
VSSPCI
PCICLK_F
PCICLK_F (33.33 MHz)
PCICLK1
VDDPCI
PCICLK2
PCICLK [17] (33.33 MHz)
APICCLK [02] (16.67 MHz)
PCICLK3
VSSPCI
PCICLK4
PCICLK5
AGPCLK [03] (66.67 MHz)
VDDPCI
PCICLK6
PCICLK7
USBCLK (48 MHz)
VSSPCI
VSSAGP
AGPCLK0
AGPCLK1
VDDAGP
VSSAGP
AGPCLK2
AGPCLK3
VDDAGP
SEL133
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDAPIC
APICCLK2
APICCLK1
APICCLK0
VSSAPIC
VDDCPU/2
CPUCLK/2
(DRCG)
CPUCLK/2
(DRCG)
VSSCPU/2
VDDCPU
CPUCLK3
CPUCLK2
VSSCPU
VDDCPU
CPUCLK1
CPUCLK0
VSSCPU
AVDD
AVSS
PCI_STOP
CPU_STOP
PWR_DWN
SPREAD
SEL1
SEL0
VDDUSB
USBCLK
VSSUSB
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07204 Rev. *A
Revised December 14, 2002



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CY2210
Pin Summary
Name
Pins
Description
VSSREF
VDDREF
VSSPCI
VDDPCI
VSSAGP
VDDAGP
VSSUSB
VDDUSB
VSSCPU
VDDCPU
VSSCPU/2
VDDCPU/2
VSSAPIC
VDDAPIC
AVSS
AVDD
XTALIN[1]
XTALOUT[1]
1
4
7, 13, 19
10, 16
20, 24
23, 27
29
31
40, 44
43, 47
48
51
52
56
38
39
5
6
3.3V Reference ground
3.3V Reference voltage supply
3.3V PCI ground
3.3V PCI voltage supply
3.3V AGP ground
3.3V AGP voltage supply
3.3V USB ground
3.3V USB voltage supply
2.5V CPU ground
2.5V CPU voltage supply
2.5V CPU/2 ground
2.5V CPU/2 voltage supply
2.5V APIC ground
2.5V APIC voltage supply
Analog ground to PLL and Core
Analog voltage supply to PLL and Core
Reference crystal input
Reference crystal feedback
CPUCLK [03] 41, 42, 45, 46
CPU clock outputs
PCICLK [17] 9, 11, 12, 14, 15, 17, 18
PCI clock outputs, synchronously running at 33.33 MHz
PCICLK_F
8
Free running PCI clock
CPUCLK/2
49, 50
CPU/2 clock outputs, drive memory clock generator
AGPCLK [03] 21, 22, 25, 26
AGP clock outputs, running at 66.66 MHz
APICCLK [02] 53, 54, 55
APIC clock outputs, running at 16.67 MHz
REFCLK [01] 2, 3
Reference clock outputs, 14.318 MHz
USBCLK
30
48-MHz USB clock output
CPU_STOP
36
Active LOW input, disables CPU and AGP clocks when asserted
PCI_STOP
37
Active LOW input, disables PCI clocks when asserted
PWR_DWN
35
Active LOW input, powers down part when asserted
SPREAD
34
Active LOW input, enables spread spectrum when asserted
SEL1
33
CPU frequency select input (See Function Table)
SEL0
32
CPU frequency select input (See Function Table)
SEL133
28
CPU frequency select input (See Function Table)
Note:
1. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF. For crystals with different CLOAD, please refer to the application note, Crystal Oscillator
Topics.
Document #: 38-07204 Rev. *A
Page 2 of 10



Part Number CY2210
Description 133-MHz Spread Spectrum Clock Synthesizer/Driver with AGP/ USB/ and DRCG Support
Maker Cypress Semiconductor - Cypress Semiconductor
Total Page 10 Pages
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