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Cypress Semiconductor Electronic Components Datasheet



CY22050

One-PLL General Purpose Flash Programmable Clock Generator



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CY22050 pdf
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CY22050
One-PLL General Purpose
Flash Programmable Clock Generator
Features
• Integrated phase-locked loop (PLL)
• Commercial and Industrial operation
• Flash-programmable
• Field-programmable
• Low-skew, low-jitter, high-accuracy outputs
• 3.3V operation with 2.5V output option
• 16-lead TSSOP
Benefits
Internal PLL to generate six outputs up to 200 MHz. Able to generate
custom frequencies from an external reference crystal or a driven source.
Performance guaranteed for applications that require an extended temper-
ature range.
Reprogrammable technology allows easy customization, quick turnaround
on design changes and product performance enhancements, and better
inventory control. Parts can be reprogrammed up to 100 times, reducing
inventory of custom parts and providing an easy method for upgrading
existing designs.
In-house programming of samples and prototype quantities is available
using the CY3672 FTG Development Kit. Production quantities are
available through Cypress’s value-added distribution partners or by using
third party programmers from BP Microsystems, HiLo Systems, and
others.
High performance suited for commercial, industrial, networking, telecomm
and other general-purpose applications.
Application compatibility in standard and low-power systems.
Industry standard packaging saves on board space.
Part Number
CY22050FC
CY22050FI
Outputs
6
6
Input Frequency Range
8 MHz–30 MHz (external crystal)
1 MHz–133 MHz (driven clock)
8 MHz–30 MHz (external crystal)
1 MHz–133 MHz (driven clock)
Output Frequency Range
80 kHz–200 MHz (3.3V)
80 KHz–166.6 MHz (2.5V)
80 kHz–166.6 MHz (3.3V)
80 KHz–150 MHz (2.5V)
Specifications
Field-programmable
commercial temperature
Field-programmable
industrial temperature
Logic Block Diagram
XIN
XOUT
OSC.
QΦ
VCO
P
PLL
Divider
Bank 1
Divider
Bank 2
Output
Select
Matrix
LCLK1
LCLK2
LCLK3
LCLK4
CLK5
CLK6
OE
Pin Configuration
VDD AVDD AVSS VSS VDDL VSSL PWRDWN
XIN
VDD
AVDD
PWRDWN
AVSS
VSSL
LCLK1
LCLK2
1
2
3
4
5
6
7
8
16 XOUT
15 CLK6
14 CLK5
13 VSS
12 LCLK4
11 VDDL
10 OE
9 LCLK3
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07006 Rev. *D
Revised January 29, 2005



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CY22050 pdf
CY22050
CY22050 Pin Summary
Name
Pin Number
Description
XIN 1 Reference Input. Driven by a crystal (8 MHz–30 MHz) or external clock (1 MHz–133 MHz).
Programmable input load capacitors allow for maximum flexibility in selecting a crystal, based
on manufacturer, process, performance, or quality.
VDD
2 3.3V voltage supply
AVDD
PWRDWN[1]
3 3.3V analog voltage supply
4 Power Down. When pin 4 is driven LOW, the CY22050 will go into shut-down mode.
AVSS
5 Analog ground
VSSL
6 LCLK ground
LCLK1
LCLK2
LCLK3
OE[1]
7 Configurable clock output 1 at VDDL level (3.3V or 2.5V)
8 Configurable clock output 2 at VDDL level (3.3V or 2.5V)
9 Configurable clock output 3 at VDDL level (3.3V or 2.5V)
10 Output Enable. When pin 10 is driven LOW, all outputs are three-stated.
VDDL
11 LCLK voltage supply (2.5V or 3.3V)
LCLK4
VSS
12 Configurable clock output 4 at VDDL level (3.3V or 2.5V)
13 Ground
CLK5
14 Configurable clock output 5 (3.3V)
CLK6
XOUT[2]
15 Configurable clock output 6 (3.3V)
16 Reference output
Functional Description
The CY22050 is the next-generation programmable FTG
(frequency timing generator) for use in networking, telecom-
munication, datacom, and other general-purpose applications.
The CY22050 offers up to six configurable outputs in a 16-pin
TSSOP, running off a 3.3V power supply. The on-chip
reference oscillator is designed to run off an 8–30-MHz crystal,
or a 1–133-MHz external clock signal.
The CY22050 has a single PLL driving 6 programmable output
clocks. The output clocks are derived from the PLL or the
reference frequency (REF). Output post dividers are available
for either. Four of the outputs can be set as 3.3V or 2.5V, for
use in a wide variety of portable and low-power applications.
Field Programming the CY22050F
The CY22050 is programmed at the package level, i.e., in a
programmer socket. The CY22050 is flash-technology based,
so the parts can be reprogrammed up to 100 times. This allows
for fast and easy design changes and product updates, and
eliminates any issues with old and out-of-date inventory.
Samples and small prototype quantities can be programmed
on the CY3672 programmer. Cypress’s value-added distri-
bution partners and third-party programming systems from BP
Microsystems, HiLo Systems, and others are available for
large-production quantities.
CyClocksRTSoftware
CyClocksRT™ is an easy-to-use software application that
allows the user to custom-configure the CY22050. Users can
specify the REF, PLL frequency, output frequencies and/or
post-dividers, and different functional options. CyClocksRT
outputs an industry-standard JEDEC file used for
programming the CY22050.
CyClocksRT can be downloaded free of charge from the
Cypress website at http://www.cypress.com.
CY3672 FTG Development Kit
The Cypress CY3672 FTG Development Kit comes complete
with everything needed to design with the CY22050 and
program samples and small prototype quantities. The kit
comes with the latest version of CyClocksRT and a small
portable programmer that connects to a PC serial port for
on-the-fly programming of custom frequencies.
The JEDEC file output of CyClocksRT can be downloaded to
the portable programmer for small-volume programming, or
for use with a production programming system for larger
volumes.
Applications
Controlling Jitter
Jitter is defined in many ways, including: phase noise,
long-term jitter, cycle-to-cycle jitter, period jitter, absolute jitter,
and deterministic jitter. These jitter terms are usually given in
terms of rms, peak-to-peak, or in the case of phase noise
dBC/Hz with respect to the fundamental frequency. Actual
jitter is dependent on XIN jitter and edge rate, number of active
outputs, output frequencies, VDDL (2.5V or 3.3V), temperature,
and output load.
Power supply noise and clock output loading are two major
system sources of clock jitter. Power supply noise can be
mitigated by proper power supply decoupling (0.1-µF ceramic
cap) of the clock and ensuring a low-impedance ground to the
Notes:
1. The CY22050 has no internal pull-up or pull-down resistors. PWRDWN and OE pins need to be driven as appropriate or tied to power or ground.
2. Float XOUT if XIN is driven by an external clock source.
Document #: 38-07006 Rev. *D
Page 2 of 9



Part Number CY22050
Description One-PLL General Purpose Flash Programmable Clock Generator
Maker Cypress Semiconductor - Cypress Semiconductor
Total Page 9 Pages
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