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Cypress Semiconductor Electronic Components Datasheet



CY14V101QS

1-Mbit (128K x 8) Quad SPI nvSRAM



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CY14V101QS pdf
CY14V101QS
1-Mbit (128K × 8) Quad SPI nvSRAM
Features
Density
1-Mbit (128K × 8)
Bandwidth
108-MHz high-speed interface
Read and write at 54 MBps
Serial Peripheral Interface
Clock polarity and phase modes 0 and 3
Multi I/O option – Single SPI (SPI), Dual SPI (DPI), and Quad
SPI (QPI)
High reliability
Infinite read, write, and RECALL cycles
One million STORE cycles to nonvolatile elements (SONOS
FLASH Quantum trap)
Data retention: 20 years at 85 °C
Read
Commands: Standard, Fast, Dual I/O, and Quad I/O
Modes: Burst Wrap, Continuous (XIP)
Write
Commands: Standard, Fast, Dual I/O, and Quad I/O
Modes: Burst Wrap
Data protection
Hardware: Through Write Protect Pin (WP)
Software: Through Write Disable instruction
Block Protection: Status Register bits to control protection
Special instructions
STORE/RECALL: Access data between SRAM and
Quantum Trap
Serial Number: 8-byte customer selectable (OTP)
Identification Number: 4-byte Manufacturer ID and Product
ID
Store from SRAM to nonvolatile SONOS FLASH Quantum Trap
AutoStore: Initiated automatically at power-down with a small
capacitor (VCAP)
Software: Using SPI instruction (STORE)
Hardware: HSB pin
Recall from nonvolatile SONOS FLASH Quantum Trap to
SRAM
Auto RECALL: Initiated automatically at power-up
Software: Using SPI instruction (RECALL)
Low-power modes
Sleep: Average current = 280 µA at 85 °C
Hibernate: Average current = 8 µA at 85 °C
Operating supply voltages
Core VCC: 2.7 V to 3.6 V
I/O VCCQ: 1.71 V to 2.0 V
Temperature range
Extended Industrial: –40 °C to 105 °C
Industrial: –40 °C to 85 °C
Packages
16-pin SOIC
24-ball FBGA
Functional Overview
The Cypress CY14V101QS combines a 1-Mbit nvSRAM with a
QPI interface. The QPI allows writing and reading the memory in
either a single (one I/O channel for one bit per clock cycle), dual
(two I/O channels for two bits per clock cycle), or quad (four I/O
channels for four bits per clock cycle) through the use of selected
opcodes.
The memory is organized as 128Kbytes each consisting of
SRAM and nonvolatile SONOS Quantum Trap cells. The SRAM
provides infinite read and write cycles, while the nonvolatile cells
provide highly reliable storage of data. Data transfers from
SRAM to the nonvolatile cells (STORE operation) take place
automatically at power-down. On power-up, data is restored to
the SRAM from the nonvolatile cells (RECALL operation). You
can also initiate the STORE and RECALL operations through
SPI instructions.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-85257 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 6, 2016



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CY14V101QS pdf
Logic Block Diagram
Status
Configuration
Registers
Serial Number
Manufacturer ID
Product ID
NC (I/O3)
HSB
SI (I/O0)
CS
SCK
WP (I/O2)
SO (I/O1)
VCC
VCCQ
VSS
VCAP
SPI/DPI/QPI
Control Logic
Write Protection
Instruction Decoder
SLEEP/HIBERNATE
Power Control
Block
Memory Control
Address & Data
CY14V101QS
Nonvolatile Array
(128K x 8)
STORE
SRAM
Array
(128K x 8)
RECALL
Document Number: 001-85257 Rev. *K
Page 2 of 55



Part Number CY14V101QS
Description 1-Mbit (128K x 8) Quad SPI nvSRAM
Maker Cypress Semiconductor - Cypress Semiconductor
Total Page 30 Pages
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