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Cypress Semiconductor Electronic Components Datasheet



CY14V101NA

1-Mbit (128 K x 8/64 K x 16) nvSRAM


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CY14V101NA pdf
CY14V101LA
CY14V101NA
1-Mbit (128 K × 8/64 K × 16) nvSRAM
1-Mbit (128 K × 8/64 K × 16) nvSRAM
Features
25 ns and 45 ns access times
Internally organized as 128 K × 8 (CY14V101LA) or 64 K × 16
(CY14V101NA)
Hands off automatic STORE on power down with only a small
capacitor
STORE to QuantumTrap non-volatile elements initiated by
software, device pin, or AutoStore on power down
RECALL to SRAM initiated by software or power up
Infinite read, write, and recall cycles
1 million STORE cycles to QuantumTrap
20 year data retention
Core VCC = 3.0 V to 3.6 V; I/O VCCQ = 1.65 V to 1.95 V
Industrial temperature
48-ball fine-pitch ball grid array (FBGA) package
Pb-free and restriction of hazardous substances (RoHS)
compliance
Functional Description
The Cypress CY14V101LA/CY14V101NA is a fast static RAM,
with a non-volatile element in each memory cell. The memory is
organized as 128 K bytes of 8 bits each or 64 K words of 16 bits
each. The embedded non-volatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
non-volatile memory. The SRAM provides infinite read and write
cycles, while independent non-volatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
non-volatile elements (the STORE operation) takes place
automatically at power down. On power-up, data is restored to
the SRAM (the RECALL operation) from the non-volatile
memory. Both the STORE and RECALL operations are also
available under software control.
Logic Block Diagram [1, 2, 3]
A5
A6
A7
A8
A9
A12
A13
A14
A15
A16
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
R
O
W
D
E
C
O
D
E
R
I
N
P
U
T
B
U
F
F
E
R
S
Quatrum Trap
1024 X 1024
STORE
RECALL
STATIC RAM
ARRAY
1024 X 1024
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10 A11
VCC VCCQ VCAP
POWER
CONTROL
STORE/RECALL
CONTROL
SOFTWARE
DETECT
HSB
A14 - A2
OE
WE
CE
BLE
BHE
Notes
1. Address A0–A16 for × 8 configuration and Address A0–A15 for × 16 configuration.
2. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .0n0et1-53953 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 4, 2011
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CY14V101NA pdf
CY14V101LA
CY14V101NA
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
SRAM Read ....................................................................... 4
SRAM Write ....................................................................... 4
AutoStore Operation ........................................................ 4
Hardware STORE Operation ............................................ 4
Hardware RECALL (Power-Up) ....................................... 5
Software STORE ............................................................... 5
Software RECALL ............................................................. 5
Preventing AutoStore ....................................................... 6
Data Protection ................................................................. 6
Noise Considerations ....................................................... 6
Best Practices ................................................................... 7
Maximum Ratings ............................................................. 8
Operating Range ............................................................... 8
DC Electrical Characteristics .......................................... 8
Data Retention and Endurance ....................................... 9
Capacitance ...................................................................... 9
Thermal Resistance .......................................................... 9
AC Test Loads ................................................................ 10
AC Test Conditions ........................................................ 10
AC Switching Characteristics ....................................... 11
SRAM Read Cycle .................................................... 11
SRAM Write Cycle ..................................................... 11
Switching Waveforms .................................................... 11
AutoStore/Power-up RECALL ....................................... 14
Switching Waveforms .................................................... 14
Software Controlled STORE/RECALL Cycle ................ 15
Switching Waveforms .................................................... 15
Hardware STORE Cycle ................................................. 16
Switching Waveforms .................................................... 16
Truth Table For SRAM Operations ................................ 17
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagrams .......................................................... 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC Solutions ......................................................... 22
Document #: 001-53953 Rev. *H
Page 2 of 22
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Part Number CY14V101NA
Description 1-Mbit (128 K x 8/64 K x 16) nvSRAM
Maker Cypress Semiconductor - Cypress Semiconductor
Total Page 22 Pages
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