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Cypress Semiconductor Electronic Components Datasheet



CY14E512J

512-Kbit (64 K x 8) Serial (I2C) nvSRAM



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CY14E512J pdf
CY14C512J
CY14B512J, CY14E512J
512-Kbit (64 K × 8) Serial (I2C) nvSRAM
512-Kbit (64 K × 8) Serial (I2C) nvSRAM
Features
512-Kbit nonvolatile static random access memory (nvSRAM)
Internally organized as 64 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using I2C
command (Software STORE) or HSB pin (Hardware STORE)
RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by I2C command (Software RECALL)
Automatic STORE on power-down with a small capacitor
(except for CY14X512J1)
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years at 85 C
High speed I2C interface
Industry standard 100 kHz and 400 kHz speed
Fast-mode Plus: 1 MHz speed
High speed: 3.4 MHz
Zero cycle delay reads and writes
Write protection
Hardware protection using Write Protect (WP) pin
Software block protection for one-quarter, one-half, or entire
array
I2C access to special functions
Nonvolatile STORE/RECALL
8 byte serial number
Manufacturer ID and Product ID
Sleep mode
Low power consumption
Average active current of 1 mA at 3.4 MHz operation
Average standby mode current of 150 µA
Sleep mode current of 8 µA
Industry standard configurations
Operating voltages:
• CY14C512J: VCC = 2.4 V to 2.6 V
• CY14B512J: VCC = 2.7 V to 3.6 V
• CY14E512J: VCC = 4.5 V to 5.5 V
Industrial temperature
8- and 16-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Overview
The Cypress CY14C512J/CY14B512J/CY14E512J combines a
512-Kbit nvSRAM[1] with a nonvolatile element in each memory
cell. The memory is organized as 64 K words of 8 bits each. The
embedded nonvolatile elements incorporate the QuantumTrap
technology, creating the world’s most reliable nonvolatile
memory. The SRAM provides infinite read and write cycles, while
the QuantumTrap cells provide highly reliable nonvolatile
storage of data. Data transfers from SRAM to the nonvolatile
elements (STORE operation) takes place automatically at
power-down (except for CY14X512J1). On power-up, data is
restored to the SRAM from the nonvolatile memory (RECALL
operation). The STORE and RECALL operations can also be
initiated by the user through I2C commands.
Configuration
Feature
CY14X512J1 CY14X512J2 CY14X512J3
AutoStore
No Yes Yes
Software STORE
Yes
Yes
Yes
Hardware STORE
No
No Yes
Slave Address pins A2, A1, A0
A2, A1
A2, A1, A0
Logic Block Diagram
VCC VCAP
Power Control
Block
Sleep
Serial Number
8x8
Manufacture ID/
Product ID
Memory Control Register
Command Register
SDA
SCL
A2, A1, A0
WP
2
I C Control Logic
Slave Address
Decoder
Control Registers Slave
Memory Slave
Memory
Address and Data
Control
Note
1. Serial (I2C) nvSRAM is referred to as nvSRAM throughout the datasheet.
Quantrum Trap
64 K x 8
SRAM
64 K x 8
STORE
RECALL
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .0n0et1-65232 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 4, 2011
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CY14E512J pdf
CY14C512J
CY14B512J, CY14E512J
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
I2C Interface ...................................................................... 4
Protocol Overview ............................................................ 4
I2C Protocol – Data Transfer ....................................... 4
Data Validity ...................................................................... 5
START Condition (S) ........................................................ 5
STOP Condition (P) .......................................................... 5
Repeated START (Sr) ....................................................... 5
Byte Format ....................................................................... 5
Acknowledge / No-acknowledge ..................................... 5
High Speed Mode (Hs-mode) ........................................... 6
Serial Data Format in Hs-mode ................................... 6
Slave Device Address ...................................................... 7
Memory Slave Device ................................................. 7
Control Registers Slave Device ................................... 7
Memory Control Register ............................................ 8
Command Register ..................................................... 8
Write Protection (WP) ....................................................... 9
AutoStore Operation ........................................................ 9
Hardware STORE and HSB pin Operation ..................... 9
Hardware RECALL (Power-Up) .................................. 9
Write Operation ............................................................... 10
Read Operation ............................................................... 10
Memory Slave Access .................................................... 10
Write nvSRAM ........................................................... 10
Current nvSRAM Read .............................................. 12
Random Address Read ............................................. 13
Control Registers Slave ................................................. 14
Write Control Registers ............................................. 14
Current Control Registers Read ................................ 15
Random Control Registers Read .............................. 15
Serial Number ................................................................. 16
Serial Number Write .................................................. 16
Serial Number Lock ................................................... 16
Serial Number Read .................................................. 16
Device ID ......................................................................... 17
Device ID Read ......................................................... 17
Executing Commands Using Command Register ....... 17
Best Practices ................................................................. 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
DC Electrical Characteristics ........................................ 19
Data Retention and Endurance ..................................... 20
Thermal Resistance ........................................................ 20
AC Test Conditions ........................................................ 21
AC Switching Characteristics ....................................... 22
nvSRAM Specifications ................................................. 23
Software Controlled STORE/RECALL Cycles .............. 24
Hardware STORE Cycle ................................................. 25
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagrams .......................................................... 27
Acronyms ........................................................................ 29
Document Conventions ................................................. 29
Units of Measure ....................................................... 29
Document History Page ................................................. 30
Sales, Solutions, and Legal Information ...................... 31
Worldwide Sales and Design Support ....................... 31
Products .................................................................... 31
PSoC Solutions ......................................................... 31
Document #: 001-65232 Rev. *B
Page 2 of 31
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Part Number CY14E512J
Description 512-Kbit (64 K x 8) Serial (I2C) nvSRAM
Maker Cypress Semiconductor - Cypress Semiconductor
Total Page 30 Pages
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