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Cypress Semiconductor Electronic Components Datasheet



CY14E064L

64 Kbit (8K x 8) nvSRAM


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CY14E064L pdf
CY14E064L
64 Kbit (8K x 8) nvSRAM
Features
25 ns and 45 ns access times
Hands off automatic STORE on power down with external
68 mF capacitor
STORE to QuantumTrap® non-volatile elements is initiated
by software, hardware or AutoStore on power down
RECALL to SRAM initiated by software or power up
www.DataSheet4UUn.cliommited READ, WRITE and RECALL cycles
10 mA typical ICC at 200 ns cycle time
1,000,000 STORE cycles to QuantumTrap
100 year data retention to QuantumTrap
Single 5V operation +10%
Commercial temperature
SOIC package
RoHS compliance
Functional Description
The Cypress CY14E064L is a fast static RAM with a
non-volatile element in each memory cell. The embedded
non-volatile elements incorporate QuantumTrap technology
producing the world’s most reliable non-volatile memory. The
SRAM provides unlimited read and write cycles, while
independent, non-volatile data resides in the highly reliable
QuantumTrap cell. Data transfers from the SRAM to the
non-volatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the non-volatile
memory. Both the STORE and RECALL operations are also
available under software control. A hardware STORE is
initiated with the HSB pin.
Logic Block Diagram
A5
A6
A7
A8
A9
A 11
A 12
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
Quantum Trap
128 X 512
STORE
STATIC RAM
ARRAY
128 X 512
RECALL
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
VCC
VCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
HSB
SOFTWARE
DETECT
-A0 A12
OE
CE
WE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-06543 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 7, 2007
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CY14E064L
Pin Configurations
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V CAP
A 12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
V SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28-SOIC
Top View
(Not To Scale)
V CC
WE
HSB
A8
A9
A 11
OE
A 10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
Pin Definitions
Pin Name IO Type
Description
A0–A12
Input
Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.
DQ0-DQ7 Input or Output Bidirectional Data IO lines. Used as input or output lines depending on operation.
WE
Input
Write Enable Input, Active LOW. When selected LOW, writes data on the IO pins to the address
location latched by the falling edge of CE.
CE
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the IO pins to tri-state.
VSS
VCC
HSB
Ground Ground for the Device. The device is connected to ground of the system.
Power Supply Power Supply Inputs to the Device.
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a non-volatile STORE operation. A weak internal pull
up resistor keeps this pin high if not connected (connection optional).
VCAP
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to
non-volatile elements.
Document Number: 001-06543 Rev. *D
Page 2 of 17
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Part Number CY14E064L
Description 64 Kbit (8K x 8) nvSRAM
Maker Cypress Semiconductor - Cypress Semiconductor
Total Page 17 Pages
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