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Cypress Semiconductor Electronic Components Datasheet



CY14B104N

4-Mbit (512K x 8/256K x 16) nvSRAM



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CY14B104N pdf
PRELIMINARY
CY14B104L, CY14B104N
4-Mbit (512K x 8/256K x 16) nvSRAM
Features
15 ns, 25 ns, and 45 ns access times
Internally organized as 512K x 8 (CY14B104L) or 256K x 16
(CY14B104N)
Hands off automatic STORE on power down with only a small
capacitor
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STORE to
QuantumTrap®
nonvolatile
elements
initiated
by
software, device pin or AutoStore® on power down
RECALL to SRAM initiated by software or power up
Infinite read, write, and recall cycles
8 mA typical ICC at 200 ns cycle time
200,000 STORE cycles to QuantumTrap
20 year data retention
Single 3V +20%, –10% operation
Commercial and industrial temperatures
FBGA and TSOP - II packages
RoHS compliance
Functional Description
The Cypress CY14B104L/CY14B104N is a fast static RAM, with
a nonvolatile element in each memory cell. The memory is
organized as 512K words of 8 bits each or 256K words of 16 bits
each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
Logic Block Diagram
VCC VCAP
[1]
Address A0 - A18
CE
OE
WE
BHE
BLE
CY14B104L
CY14B104N
[1]
DQ0 - DQ7
HSB
VSS
Note
1. Address A0 - A18 and Data DQ0 - DQ7 for x8 configuration, Address A0 - A17 and Data DQ0 - DQ15 for x16 configuration.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-07102 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 02, 2008
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CY14B104N pdf
PRELIMINARY
CY14B104L, CY14B104N
Pinouts
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Figure 1. Pin Diagram - 48 FBGA
48-FBGA
(x16)
Top View
(not to scale)
48-FBGA
(x8)
Top View
(not to scale)
12 34 56
12
34
56
BLE OE A0 A1 A2 NC
DQ8 BHE A3 A4 CE DQ0
DQ9 DQ10 A5 A6 DQ1 DQ2
VSS DQ11 A17 A7 DQ3 VCC
VCC DQ12 VCAP A16 DQ4 VSS
DQ14 DQ13 A14 A15 DQ5 DQ6
DQ15 HSB A12 A13 WE DQ7
[2]
NC
A8
A9
A10 A11 NC
A
B
C
D
E
F
G
H
NC OE A0 A1 A2 NC
NC NC A3 A4 CE NC
DQ0 NC A5 A6 NC DQ4
VSS DQ1 A17 A7 DQ5 VCC
VCC DQ2 VCAP A16 DQ6 VSS
DQ3 NC A14 A15 NC DQ7
NC HSB A12 A13 WE NC
A18
A8
A9
A10
A11
[2]
NC
A
B
C
D
E
F
G
H
Figure 2. Pin Diagram - 44 TSOP II
A0
A1
A2
A3
A4
CE
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9 44 - TSOP II
10 (x16)
11
12 Top View
13 (not to scale)
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
BHE
BLE
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ11
DQ10
DQ9
DQ8
VCAP
A14
A13
A12
A11
A10
NC
NC[3]
A0
A1
A2
A3
A4
CE
DQ0
DQ1
VCC
VSS
DQ2
DQ3
WE
A5
A6
A7
A8
A9
NC
NC
1
2
3
4
5
6
7
8
9 44 - TSOP II
10 (x8)
11
12 Top View
13 (not to scale)
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
HSB
NC
NC[2]
A18
A17
A16
A15
OE
DQ7
DQ6
VSS
VCC
DQ5
DQ4
VCAP
A14
A13
A12
A11
A10
NC
NC
Notes
2. Address expansion for 8 Mbit. NC pin not connected to die.
3. Address expansion for 16 Mbit. NC pin not connected to die.
Document #: 001-07102 Rev. *F
Page 2 of 22
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Part Number CY14B104N
Description 4-Mbit (512K x 8/256K x 16) nvSRAM
Maker Cypress Semiconductor - Cypress Semiconductor
Total Page 22 Pages
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