I2C Clock Distribution Buffer for Three Banks of Mobile SDRAM
• 7 output buffer for high clock fanout applications.
• Output may be individually disabled with I2C
• VDD = 3.3 volts
• Output frequency range 10 MHz to 100 MHz
• <250ps skew between output clocks.
• 16-pin SSOP and TSSOP package.
The device is a high fanout system clock buffer. Its
primary application is to distribute clocks needed to
support a wide range of applications such as SDRAM
clocks. This device provides low skew distribution
clock heavily loaded. One important application of
this component is where long traces are used to
transport clocks from their generating devices to their
loads. The creation of EMI and the degradation of
waveform rise and fall times is greatly reduces by
running a single reference clock trace to this device
and then using it to these devices EMI is therefore
minimized and board real estate is saved.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
Document#: 38-07024 Rev. **
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