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Cypress Semiconductor Electronic Components Datasheet



C9835

Low-EMI Clock Generator


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C9835 pdf
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C9835
Low-EMI Clock Generator for Intel®
Mobile 133-MHz/3 SO-DIMM Chipset Systems
Features
• Meets Intel’sMobile 133.3MHz Chipset
• Three CPU Clocks (66.6/100/133.3 MHz, 2.5V)
• Six SDRAM Clocks, 1-DCLK (100/133.3 MHz, 3.3V)
• Seven PCI Clocks (33MHz, 3.3V), one free running
• Two IOAPIC clocks, synchronous to CPU clock (33.3
MHz, 2.5V)
• One REF Clock
• Two 48-MHz fixed non-SSCG clocks (USB and DOT)
• Three 3V66 clocks (66.6 MHz, 3.3V) ICH, HUBLINK, and
AGP memory
• One selectable frequency for VCH video channel clock
(48-MHz non-SSCG, 66.6-MHz CPU-SSCG, 3.3V)
• Power management using power-down, CPU stop, and
PCI stop pins
• Three function select pins (include test-mode select)
• Cypress Spread Spectrum for best electromagnetic
interference (EMI) reduction
• SMBUS support with readback
• 56-pin SSOP and TSSOP packages
Table 1. Function Table[1]
TEST#
0
0
1
1
1
1
SEL1
X
X
0
0
1
1
SEL0
0
1
0
1
0
1
CPU(0:2)
Hi-Z
TCLK/2
66.6
100.0
133.3
133.3
SDRAM(0:5)
DCLK
Hi-Z
TCLK/2
100.0[2]
100.0[2]
133.3
100.0[2]
3V66(0:2)
Hi-Z
TCLK/3
66.6
66.6
66.6
66.6
PCIF(1:6) 48M(0:1) REF IOAPIC(0:10)
Hi-Z
TCLK/6
33.3
33.3
33.3
33.3
Hi-Z
TCLK/2
48
48
48
48
Hi-Z
TCLK
14.318
14.318
14.318
14.318
Hi-Z
TCLK/6
33.3
33.3
33.3
33.3
Note:
1. These are the frequencies that are selectable after power up using the SEL1 and SEL0 hardware pins. Other frequencies may be chosen using the devices
SMBUS interface. See the expanded frequency for a complete listing of all of the availible frequencies.
2. Will be set to 133MHz, when SMBUS Byte3, Bit 0 is set to logic 1.
Block Diagram
Pin Configuration
X IN
XO U T
TEST#
S E L 0 ,1
P C I_ S T P #
C P U _S T P #
PD#
S C LK
SDATA
36pF
36pF
IO A P IC
CPU
R in
tris ta te
s0
PD#
SDRAM
3V66
i2 c -c lk
i2 c -d a ta
PLL1
R in
48
PD#
i2 c -c lk
i2 c -d a ta
PLL2
PCI
VDD
1
VDD
1
VDDI
REF
VC H _C LK
2 IO A P IC (0 ,1 )
VDDC
3 C P U (0:2 )
VDDS
6
VDD
3
VDDP
S D R A M (0 :5 )
3 V 6 6 (0 :2 )
P C I_ F
VDDP
6 P C I(1 :6 )
VDD
2 4 8 M (0 ,1 )
VDDS
1 D C LK
REF
VDD
XIN
XOUT
VSS
VSS
3V66_0
3V66_1
3 V 66 _2(A G P )
VDD
P C I_S T P #
PCI_F
PCI1
VSS
PCI2
PCI3
VDDP
PCI4
PCI5
PCI6
VSS
AVDD
AVSS
VSS
4 8M 0(U S B )
48 M 1(D O T )
VDD
SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 VSS
55 IOAPIC0
54 IOAPIC1
53 VDDI
52 CPU0
51 VDDC
50 CPU1
49 CPU2
48 VSS
47 VSS
C
46
45
SDRAM0
SDRAM1
9 44 VDDS
8 43 SDRAM2
3
42
41
SDRAM3
VSS
5 40 SDRAM4
39 SDRAM5
38 DCLK
37 VDDS
36 VCH_CLK
35 VDD
34 CPU_STP#
33 TEST#
32 PD#
31 SCLK
30 SDATA
29 SEL1
Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600
Document #: 38-07303 Rev. **
Revised April 5, 2002



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C9835 pdf
C9835
Pin Description[3]
Pin
Name
PWR
Description
1 REF
VDD 3.3V 14.318 MHz clock output
3 XIN
VDD Oscillator buffer input. Connect to a crystal or to an external clock.
4
49, 50, 52
XOUT
CPU(0:2)
VDD
Oscillator buffer output. Connect to a crystal. Do not connect when an external
clock is applied at XIN.
VDDC 2.5V Host bus clock outputs
7, 8, 9
3V66(0:2)
VDD 3.3V Fixed 66.6 MHz clock outputs
12 PCI_F
VDDP
3.3V PCI clock output. This clock continues to run when PCI_STP# is at a logic
low level.
13, 15, 16, 18,
19, 20
PCI (1:6)
3.3V PCI clock outputs. These clocks synchronously stop in a low state when
VDDP PCI_STP# is brought to a logic low level. They synchronously resume running
when PCI_STP# is brought to a logic high state.
25, 26
48M(0,1)
VDD 3.3V Fixed 48 MHz clock outputs
36
VCH_CLK
VDD
3.3V selectable 66.6 MHz or 48 MHz clock output to VCH. Spread spectrum
applies only when 66.6 MHz is selected. Select via SMBUS, byte 4 bit7.
CPU0 stop clock control input. Stops only CPU0 in a low state when asserted
34
CPU_STP#
VDD low. Using this pin to start and stop CPU0 clock insures synchronous (no short or
long clocks) transitioning of this clock.
PCI stop clock control input. When this signal is at a logic low level (0), all PCI
11
PCI_STP#
VDD
clocks (except PCI_F) stop at a logic low level. Using this pin to start and stop PCI
clocks insures synchronous (no short or long clocks) transitioning of these clocks.
This pin has no effect on the PCI_F clock.
28, 29
SEL(0,1)
VDD
3.3V LVTTL inputs for logic selection. These pins have Internal pull-ups,
typically 250k (range 200k to 800k).
30 SDATA
VDD
Serial data input pin. Conforms to the SMBUS specification of a Slave
Receive/Transmit device. This pin is an input when receiving data. It is an open
drain output when acknowledging or transmitting data. See 2-Wire SMBUS
Control Interface on page 7.
31 SCLK
VDD
Serial clock input pin. Conforms to the SMBUS specification. See 2-Wire
SMBUS Control Interface on page 7.
32 PD#
3.3V LVTTL-compatible input. When held LOW, the device enters a power down
VDD mode. This pin has an Internal Pull-Up. See Power Management Functions on
page 3.
33 TEST#
VDD 3.3V LVTTL compatible input for selecting test mode. See Table 1.
38 DCLK
VDDS
3.3V SDRAM feedback clock output. See Table 1 for frequency selection. See
Figure 4 for timing relationship.
39, 40, 42, 43,
45, 46
SDRAM(0:5)
VDDS 3.3V SDRAM clock outputs
54, 55
IOAPIC(0,1)
VDDI 2.5V IOAPIC clock outputs. See Figure 4 for timing relationships.
37, 44
VDDS
3.3V Power for SDRAM and DCLK clock output buffers
17 VDDP
3.3V Power for PCI clock output buffers
53 VDDI
2.5V Power for IOAPIC clock output buffers
51 VDDC
2.5V Power for CPU clock output buffers
2, 10, 27, 35 VDD
3.3V Common power supply
22 AVDD
Analog power
23 AVSS
Analog ground
5, 6, 14, 21, 24,
41, 47, 48, 56
VSS
Common ground pins
Note:
3. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin. If these bypass capacitors are not close to the pins their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
Document #: 38-07303 Rev. **
Page 2 of 18



Part Number C9835
Description Low-EMI Clock Generator
Maker Cypress Semiconductor - Cypress Semiconductor
Total Page 18 Pages
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