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Cypress Semiconductor Electronic Components Datasheet



C9531

PCIX I/O System Clock Generator with EMI Control Features



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C9531 pdf
C9531
PCIX I/O System Clock Generator with EMI Control Features
Features
• Dedicated clock buffer power pins for reduced noise,
crosstalk and jitter
• Input clock frequency of 25 MHz to 33 MHz
• Output frequencies of XINx1, XINx2, XINx3 and XINx4
• One output bank of 5 clocks.
• One REF XIN clock output.
• SMBus clock control interface for individual clock
disabling and SSCG control
• Output clock duty cycle is 50% (± 5%)
• < 250 ps skew between output clocks within a bank
• Output jitter <175 ps
• Spread Spectrum feature for reduced electromagnetic
interference (EMI)
• OE pin for entire output bank enable control and
testability
• 28-pin SSOP and TSSOP packages
Block Diagram
Table 1. Test Mode Logic Table[1]
OE
HIGH
HIGH
HIGH
HIGH
LOW
Input Pins
S1
LOW
LOW
HIGH
HIGH
X
S0
LOW
HIGH
LOW
HIGH
X
Output Pins
CLK
REF
XIN XIN
2 * XIN
XIN
3 * XIN
XIN
4 * XIN
XIN
Three-state Three-state
Pin Configuration
SSCG#
SSCG
Logic
XIN
XOUT
/N 1
0
SDATA
SCLK
IA(0:2)
S(0,1)
I2C
Control
Logic
CLK0
CLK1
CLK2
CLK3
CLK4
OE
GOOD#
REF
Note:
1. XIN is the frequency of the clock on the device’s XIN pin.
REF
VDD
XIN
XOUT
VSS
S0
S1
GOOD#
VSS
IA0
IA1
IA2
VDDA
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 SDATA
27 SCLK
26 VSS
25 VDDP
24 CLK0
23 CLK1
22 CLK2
21 VSS
20 VDDP
19 CLK3
18 CLK4
17 VDDA
16 VSS
15 SSCG#
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07034 Rev. *D
Revised May 12, 2003



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C9531 pdf
C9531
Pin Description[3]
Pin[2]
Name
3 XIN
4 XOUT
1 REF
14* OE
24, 23, 22, 19, 18 CLK(0:4)
8 GOOD#
6*, 7*
S(0,1)
20, 25
10*, 11*, 12*
15*
VDDP
IA(0:2)
SSCG#
28
27
13, 17
2
5, 9, 16, 21, 26
SDATA
SCLK
VDDA
VDD
VSS
PWR[4]
VDDA
VDDA
VDD
VDD
VDDP
VDD
VDD
VDD
VDD
VDD
VDD
I/O
I
O
O
I
O
O
I
PWR
I
I
I/O
I
I
PWR
PWR
Description
Crystal Buffer Input Pin. Connects to a crystal, or an external clock
source. Serves as input clock TCLK, in Test mode.
Crystal Buffer Output Pin. Connects to a crystal only. When a Can
Oscillator is used or in test mode, this pin is kept unconnected.
Buffered inverted outputs of the signal applied at Xin, typically
33.33 or 25.0 MHz.
Output Enable for Clock Bank. Causes the CLK (0:4) output clocks
to be in a three-state condition when driven to a logic low level.
A bank of five XINx1, XINx2, XINx3 and XINx4 output clocks.
When his output signal is a logic low level, it indicates that the output
clocks of the bank are locked to the input reference clock. This
output is latched.
Clock Bank Selection Bits. These control the clock frequency that will
be present on the outputs of the bank of buffers. See table on page
one for frequency codes and selection values.
3.3V common power supply pin for all PCI clocks CLK (0:4).
SMBus Address Selection Input Pins. See Table 3 on page 3.
Spread Spectrum Clock Generator. Enables Spread Spectrum clock
modulation when at a logic low level, see Spread Spectrum Clocking
on page 6.
Data for the Internal SMBus Circuitry. See Table 3 on page 3.
Clock for the Internal SMBus Circuitry. See Table 3 on page 3.
Power for Internal Analog Circuitry. This supply should have a
separately decoupled current source from VDD.
Power supply for internal core logic.
Ground pins for the device.
Notes:
2. Pin numbers ending with * indicate that they contain device internal pull-up resistors that will insure that they are sensed as a logic 1 if no external circuitry is
connected to them.
3. A bypass capacitor (0.1µF) should be placed as close as possible to each VDD pin. If these bypass capacitors are not close to the pins their high frequency
filtering characteristic will be cancelled by the lead inductance of the trace.
4. PWR = Power connection, I = Input, O = Output and I/O = both input and output functionality of the pin(s).
Serial Data Interface
Data Protocol
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required.
The clock driver serial protocol accepts block write a opera-
tions from the controller. The bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. The C9531 does not support the Block Read
function.
The block write protocol is outlined in Table 2. The addresses
are listed in Table 3.
Document #: 38-07034 Rev. *D
Page 2 of 10



Part Number C9531
Description PCIX I/O System Clock Generator with EMI Control Features
Maker Cypress Semiconductor - Cypress Semiconductor
Total Page 10 Pages
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