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Atmel Electronic Components Datasheet



AT24CS128

2-Wire Serial EEPROMs


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AT24CS128 pdf
Features
One-time Programmable (OTP) Feature
Low-voltage and Standard-voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)
Internally Organized 16,384 x 8 and 32,768 x 8
2-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility
Write Protect Pin for Hardware and Software Data Protection
64-byte Page Write Mode (Partial Page Writes Allowed)
Self-timed Write Cycle (5 ms typical)
High Reliability
– Endurance: 100,000 Write Cycles
– Data Retention: 40 Years
– ESD Protection: >4000V
Automotive Grade and Extended Temperature Devices Available
8-pin JEDEC PDIP and 8-pin JEDEC and EIAJ SOIC Packages
Description
The AT24CS128/256 provides 131,072/262,144 bits of serial electrically-erasable and
programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8
bits each. The device’s cascadable feature allows up to 4 devices to share a common
2-wire bus. The device also features a one-time programmable 2048-bit array, which
once enabled, becomes read-only and cannot be overwritten. If not enabled, the OTP
section will function as part of the normal memory array. The device is optimized for
use in many industrial and commercial applications where low-power and low-voltage
operation are essential. The devices are available in space-saving 8-pin JEDEC PDIP
(AT24CS128/256), 8-pin EIAJ (AT24CS128/256), 8-pin JEDEC SOIC (AT24CS128)
packages. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V
to 5.5V) and 1.8V (1.8V to 3.6V) versions.
Pin Configurations
Pin Name
A0 - A2
SDA
SCL
WP
Function
Address Inputs
Serial Data
Serial Clock Input
Write Protect
PDIP
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
Pin SOIC
2-wire Serial
EEPROMs
with Permanent
Software Write
Protect
128K (16,384 x 8)
256K (32,768 x 8)
AT24CS128
AT24CS256
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
Rev. 1152B–05/01
1



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AT24CS128 pdf
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Block Diagram
*NOTICE:
Stresses beyond those listed under Absolute
Maximum Ratingsmay cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
A2
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive
edge clock data into each EEPROM device and negative
edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for
serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A1 and
A0 pins are device address inputs that are hardwired or left
not connected for hardware compatibility with AT24C32/64.
When the pins are hardwired, as many as four 128K/256K
devices may be addressed on a single bus system (device
addressing is discussed in detail under the Device
Addressing section). When the pins are not hardwired, the
default A1 and A0 are zero. The A2 device address input is
a dont careinput.
WRITE PROTECT (WP): The write protect input, when tied
to GND, allows normal write operations. When WP is tied
high to VCC, all write operations to the memory are inhib-
ited. If left unconnected, WP is internally pulled down to
GND. Switching WP to VCC prior to a write operation cre-
ates a software write protect function.
Memory Organization
AT24CS128/256, 128K/256K SERIAL EEPROM: The
128K/256K is internally organized as 256/512 pages of 64-
bytes each. Random word addressing requires a 14/15-bit
data word address.
2 AT24CS128/256



Part Number AT24CS128
Description 2-Wire Serial EEPROMs
Maker ATMEL Corporation - ATMEL Corporation
Total Page 13 Pages
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