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Atmel Electronic Components Datasheet



AT17N010-10CI

FPGA Configuration Memory


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AT17N010-10CI pdf
Features
EE Programmable 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-, 2,097,152 x 1-, and
4,194,304 x 1-bit Serial Memories Designed to Store Configuration Programs for Field
Programmable Gate Arrays (FPGAs)
Available as a 3.3V (±10%) Commercial and Industrial Version
Simple Interface to SRAM FPGAs
Pin Compatible with Xilinx® XC17SXXXA and XC17SXXXXL PROMs
Compatible with Xilinx Spartan®-II, Spartan-IIE and Spartan XL FPGAs in Master Serial
Mode
Very Low-power CMOS EEPROM Process
Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC
Packages), 8-lead PDIP, 8-lead SOIC, 20-lead SOIC and 44-lead TQFP Packages for a
Specific Density
Low-power Standby Mode
High-reliability
– Endurance: Minimum 10 Write Cycles
– Data Retention: 20 Years at 85°C
Description
The AT17N series FPGA Configuration EEPROM (Configurators) provide an easy-to-
use, cost-effective configuration memory for Field Programmable Gate Arrays. The
AT17N series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-lead
SOIC and 44-lead TQFP, see Table 1. The AT17N series Configurators uses a simple
serial-access procedure to configure one or more FPGA devices.
The AT17N series configurators can be programmed with industry-standard program-
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable and
factory programming.
Table 1. AT17N Series Packages
Package
AT17N256
AT17N512/
AT17N010
AT17N002
AT17N040
8-lead LAP
Yes
Yes –
8-lead PDIP
8-lead SOIC
Yes Yes
Yes Use 8-lead LAP(1) Use 8-lead LAP(1)
20-lead SOIC
Yes
Yes
Yes –
44-lead TQFP
Yes Yes
Note:
1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-
lead SOIC package is not available for the AT17N512/010/002 devices, it is possi-
ble to use an 8-lead LAP package instead.
FPGA
Configuration
Memory
AT17N256
AT17N512
AT17N010
AT17N002
AT17N040
3.3V
System Support
Rev. 3020A–CNFG–05/03
1



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AT17N010-10CI pdf
Pin Configuration
8-lead LAP
DATA 1
CLK 2
RESET/OE 3
CE 4
8 VCC
7 VCC (SER_EN)
6 DC
5 GND
DATA
CLK
RESET/OE
CE
8-lead SOIC
1 8 VCC
2 7 VCC (SER_EN)
3 6 DC
4 5 GND
8-lead PDIP
DATA
CLK
RESET/OE
CE
1
2
3
4
8 VCC
7 VCC (SER_EN)
6 DC
5 GND
20-lead SOIC
DATA
NC
CLK
NC
NC
NC
NC
RESET/OE
NC
CE
1
2
3
4
5
6
7
8
9
10
20 VCC
19 NC
18 VCC (SER_EN)
17 NC
16 NC
15 NC
14 NC
13 DC
12 NC
11 GND
2 AT17N256/512/010/002/040
3020A–CNFG–04/10/03



Part Number AT17N010-10CI
Description FPGA Configuration Memory
Maker ATMEL Corporation - ATMEL Corporation
Total Page 18 Pages
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AT17N010-10CI pdf
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