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FPGA Configuration EEPROM Memory

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AT17LV010A pdf
Note 1.
AT17LV65A, AT17LV128A,
and AT17LV256A are
Not Recommended for New
Designs (NRND) and are
Replaced by AT17LV512A.
AT17LV65A(1), AT17LV128A(1), AT17LV256A(1)
AT17LV512A, AT17LV010A, AT17LV002A
FPGA Configuration EEPROM Memory
3.3V and 5V System Support
EE Programmable Serial Memories Designed to Store Configuration Programs for
Altera® FLEX® and APEXField Programmable Gate Arrays (FPGA)
̶ 65,536 x 1-bit(1)
̶ 262,144 x 1-bit(1)
̶ 1,048,576 x 1-bit
̶ 131,072 x 1-bit(1)
̶ 524,288 x 1-bit
̶ 2,097,152 x 1-bit
Supports both 3.3V and 5.0V Operating Voltage Applications
In-System Programmable (ISP) via 2-wire Bus
Simple Interface to SRAM FPGAs
Compatible with the Atmel® AT6000, AT40K and AT94K Devices, Altera FLEX,
APEX Devices, ORCA® FPGAs, Xilinx® XC3000, XC4000, XC5200, Spartan®,
VirtexFPGAs, Motorola MPA1000 FPGAs
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
Very Low-power CMOS EEPROM Process
Programmable Reset Polarity
8-lead PDIP and 20-lead PLCC Packages (Pin-compatible Across Product Family)
Emulation of the Atmel AT24C Serial EEPROMs
Low-power Standby Mode
̶ Endurance: 100,000 Write Cycles
̶ Data Retention: 90 Years for Industrial Parts (at 85C)
Green (Pb/Halide-free/RoHS Compliant) Package Options Available
The Atmel® AT17LVxxxA FPGA configuration EEPROMs (Configurators) provide an
easy-to-use, cost-effective configuration memory solution for FPGAs. The
AT17LVxxxA are packaged in 8-lead PDIP and 20-lead PLCC options. The
AT17LVxxxA configurator uses a simple serial-access procedure to configure one or
more FPGA devices. The user can select the polarity of the reset function by
programming four EEPROM bytes. These devices support a write protection
mechanism within its programming mode.
The AT17LVxxxA configurators can be programmed with industry-standard
programmers, the Atmel ATDH2200E Programming Kit, or the Atmel ATDH2225 ISP
Table 1. AT17LVxxxA Packages
8-lead PDIP
20-lead PLCC

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AT17LV010A pdf
1. Pin Configuration and Descriptions
Table 1-1. Pin Descriptions
Pin Description
Three-state DATA Output for Configuration. Open-collector bi-directional pin for programming.
Clock Output or Clock Input. Rising edges on DCLK increment the internal address counter and present
the next bit of data to the DATA pin. The counter is incremented only if the RESET/OE input is held High,
the nCS input is held Low, and all configuration data has not been transferred to the target device
(otherwise, as the master device, the DCLK pin drives Low).
Write Protect (1). This pin is used to protect portions of memory during programming, and it is disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading operations.
This pin is only available on the AT17LV512A/010A/002A.
RESET (Active Low) / Output Enable (Active High) when SER_EN is High. A Low logic level resets the
address counter. A High logic level (with nCS Low) enables DATA and permits the address counter to
count. In the mode, if this pin is Low (reset), the internal oscillator becomes inactive and DCLK drives Low.
The logic polarity of this input is programmable and must be programmed active High (RESET active Low)
by the user during programming for Altera applications.
Write Protect Input (when nCS is Low) during programming only (SER_EN Low). When WP is Low, the
entire memory can be written. When WP is enabled (High), the lowest block of the memory cannot be
written. This pin is only available on AT17LV65A/128A/256A devices.
Chip Select Input (Active Low). A Low input (with OE High) allows DCLK to increment the address
counter and enables DATA to drive out. If the AT17LVxxxA is reset with nCS Low, the device initializes as
the first (and master) device in a daisy-chain. If the AT17LVxxxA is reset with nCS High, the device
initializes as a subsequent AT17LVxxxA in the chain.
Ground. A 0.2μF decoupling capacitor between VCC and GND is recommended.
Cascade Select Output (Active Low). This output goes Low when the address counter has reached its
maximum value. In a daisy-chain of AT17LVxxxA devices, the nCASC pin of one device is usually
connected to the nCS input pin of the next device in the chain, which permits DCLK from the master
configurator to clock data from a subsequent AT17LVxxxA device in the chain. This feature is not available
on the AT17LV65A (NRND).
Device Selection Input, A2. This is used to enable (or select) the device during programming (i.e., when
SER_EN is Low). A2 has an internal pull-down resistor.
Open Collector Reset State Indicator. Driven Low during power-on reset cycle, released when power-
up is complete. (recommended 4.7kpull-up on this pin if used).
Serial Enable must be held High during FPGA loading operations. Bringing SER_EN Low enables the 2-
wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied to VCC.
Power Supply. 3.3V (±10%) and 5.0V (±10%) power supply pin.
2 AT17LV65A/128A/256A/512A/002A [DATASHEET]

Part Number AT17LV010A
Description FPGA Configuration EEPROM Memory
Total Page 16 Pages
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