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FPGA Configuration E2PROM

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AT17C65 pdf
AT17 Series
E2 Programmable 65,536 x 1, 131,072 x 1, and 262,144 x 1 bit Serial Memories Designed
To Store Configuration Programs For Programmable Gate Arrays
Simple Interface to SRAM FPGAs Requires Only One User I/O Pin
Compatible With AT6000 FPGAs, ATT3000 FPGA, EPF8000 FPGAs, ORCA FPGAs,
XC2000, XC3000, XC4000, XC5000 FPGAs, MPA1000
Cascadable To Support Additional Configurations or Future Higher-density Arrays
(17C128 and 17C256 only)
Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available In the Space-efficient Plastic DIP or Surface-mount
PLCC and SOIC Packages
In-System Programmable Via 2-Wire Bus
Emulation of 24CXX Serial EPROMs
Available in 3.3V ± 10% LV Version
The AT17C65/128/256 and AT17LV65/128/256 (AT17 Series) FPGA Configuration
EEPROMS (Configurator) provide an easy-to-use, cost-effective configuration mem-
ory for Field Programmable Gate Arrays. The AT17 Series is packaged in the 8-pin
DIP and the popular 20-pin PLCC and SOIC. The AT17 Series family uses a simple
serial-access procedure to configure one or more FPGA devices. The AT17 Series
organization supplies enough memory to configure one or multiple smaller FPGAs.
Using a special feature of the AT17 Series, the user can select the polarity of the reset
function by programming a special EEPROM bit.
The AT17 Series can be programmed with industry standard programmers.
65K, 128K and 256K
Pin Configurations
20-pin PLCC
20-Pin SOIC
8-Pin DIP

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AT17C65 pdf
Controlling The AT17 Series Serial EEPROMs
Most connections between the FPGA device and the Serial
EEPROM are simple and self-explanatory.
• The DATA output of the AT17 Series drives DIN of the
FPGA devices.
• The master FPGA CCLK output drives the CLK input of
the AT17 Series.
tion cycle. If a system reset is applied to the FPGA, it will
abort the original configuration and then reset itself for a
new configuration, as intended. Of course, the AT17 Series
does not see the external reset signal and will not reset its
internal address counters and, consequently, will remain
out of sync with the FPGA for the remainder of the configu-
ration cycle.
• The CEO output of any AT17C/LV128/256 drives the CE
input of the next AT17C/LV128/256 in a cascade chain of
• SER_EN must be connected to VCC.
There are, however, two different ways to use the inputs
CE and OE, as shown in the AC Characteristics wave-
Condition 1
The simplest connection is to have the FPGA D/P output
drive both CE and RESET/OE in parallel (Figure 1). Due to
its simplicity, however, this method will fail if the FPGA
receives an external reset condition during the configura-
Condition 2
The FPGA D/P output drives only the CE input of the AT17
Series, while its OE input is driven by the inversion of the
input to the FPGA RESET input pin. This connection works
under all normal circumstances, even when the user aborts
a configuration before D/P has gone High. A High level on
the RESET/OE input to the AT17C/LVxxx – during FPGA
reset – clears the Configurator's internal address pointer,
so that the reconfiguration starts at the beginning. The
AT17 Series does not require an inverter since the RESET
polarity is programmable.
Block Diagram
2 AT17 Series

Part Number AT17C65
Description FPGA Configuration E2PROM
Maker ATMEL Corporation - ATMEL Corporation
Total Page 10 Pages
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