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Atmel Electronic Components Datasheet



AT17C512A

FPGA Serial Configuration Memories



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AT17C512A pdf
Features
Serial EEPROM Family for Configuring Altera FLEX® 10K Devices
Simple, Easy-to-use 4-pin Interface
E2 Programmable 1M Bit Serial Memories Designed To Store Configuration Programs
For Programmable Gate Arrays
Cascadable To Support Additional Configurations or Future Higher-density Arrays
Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available in the Space-efficient Surface-mount PLCC Package
In-System Programmable Via 2-Wire Bus
Emulation of 24CXX Serial EPROMs
Available in 3.3V ± 10% LV and 5V ± 5% C Versions
Description
The AT17C512/010A and AT17LV512/010A (AT17A Series) FPGA Configuration
EEPROMs (Configurators) provide and easy-to-use, cost-effective configuration
memory for programming Altera FLEX Field Programmable Gate Arrays, FPGA, (the
“devices”). The AT17A Series is packaged in the popular 20-pin PLCC package. The
AT17A Series family uses a simple serial-access procedure to configure one or more
FPGA devices. The AT17A Series organization supplies enough memory to configure
one or multiple smaller FPGAs. Using a special feature of the AT17A Series, the user
can select the polarity of the reset function by programming an EEPROM byte. The
AT17C/LV512/010A parts generate their own internal clock and can be used as a sys-
tem “master” for loading the FPGA devices.
The Atmel devices also supports a system friendly READY pin and a write protect
mechanism. The READY pin is used to simplify system power-up considerations. The
WP1 pin is used to protect part of the device memory during in-system programming.
The AT17A Series can be programmed with industry standard programmers.
FPGA Serial
Configuration
Memories
AT17C512A
AT17LV512A
AT17C010A
AT17LV010A
Pin Configurations
20-Pin PLCC
DCLK
WP1
NC
NC
RESET/OE
4
5
6
7
8
18 SER_EN
17 NC
16 NC
15 READY
14 NC
Rev. 0974A–04/98
1



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AT17C512A pdf
Block Diagram
SER_EN
OSC
CONTROL
OSC
PROGRAMMING
MODE LOGIC
ROW
ADDRESS
COUNTER
11
ROW
DECODER
BIT
COUNTER
5
TC
PROGRAMMING
DATA SHIFT
REGISTER
24/32
EEPROM
CELL
MATRIX
24/32
COLUMN
DECODER
DCLK
OE
nCS
nCASC
DATA
Device Configuration
The control signals for configuration EEPROMs–nCS, OE,
and DCLK–interface directly with the FPGA device control
signals. All FPGA devices can control the entire configura-
tion process and retrieve data from the configuration
EEPROM without requiring an external intelligent control-
ler.
The configuration EEPROM device’s OE and nCS pins
control the tri-state buffer on the DATA output pin and
enable the address counter and the oscillator. When OE is
driven low, the configuration EEPROM device resets the
address counter and tri-states its DATA pin. The nCS pin
controls the output of the AT17A Series. If nCS is held high
after the OE reset pulse, the counter is disabled and the
DATA output pin is tri-stated. When nCS is driven low, the
counter and the DATA output pin are enabled. When OE is
driven low again, the address counter is reset and the
DATA output pin is tri-stated, regardless of the state of the
nCS.
When the configurator has driven out all of its data and
nCASC is driven low, the device tri-states the DATA pin to
avoid contention with other configurators. Upon power-up,
the address counter is automatically reset.
FPGA Device Configuration
FPGA devices can be configured with an AT17A Series
EEPROM. The AT17A Series device stores configuration
data in its EEPROM array and clocks the data out serially
with its internal oscillator. The OE, nCS, and DCLK pins
supply the control signals for the address counter and the
output tri-state buffer. The AT17A Series device sends a
serial bitstream of configuration data to its DATA pin, which
is connected to the DATA0 input pin on the FPGA device.
When configuration data for a FPGA device exceeds the
capacity of a single AT17A Series device, multiple AT17A
Series devices can be serially linked together. When multi-
ple AT17A Series devices are required, the nCASC and
nCS pins provide handshaking between the AT17A Series
devices.
The position of an AT17A Series device in a chain deter-
mines its operation. The first AT17A Series device in a
Configurator chain is powered up or reset with nCS low and
is configured for FPGA devices protocol. This AT17A
Series device supplies all clock pulses to one or more
FPGA devices and to any downstream AT17A Series dur-
ing configuration. The first AT17A Series device also pro-
vides the first stream of data to the FPGA devices during
2 AT17C/LV/512A/010A



Part Number AT17C512A
Description FPGA Serial Configuration Memories
Maker ATMEL Corporation - ATMEL Corporation
Total Page 11 Pages
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