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Atmel Electronic Components Datasheet



AT17C512

FPGA Configuration E2PROM Memory


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AT17C512 pdf
Features
E2 Programmable 524,288 x 1 and 1,048,576 x 1 bit Serial Memories Designed To Store
Configuration Programs For Field Programmable Gate Arrays (FPGA)
Simple Interface to SRAM FPGAs
Compatible With Atmel AT6000, AT40K FPGAs, Altera EPF8K, EPF10K,
EPF6K FPGAs, ORCA FPGAs, Xilinx XC3000, XC4000, XC5200 FPGAs, Motorola
MPA1000 FPGAs
Cascadable To Support Additional Configurations or Future Higher-density Arrays
Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available In PLCC Package (Pin Compatable across Product Family)
In-System Programmable Via 2-Wire Bus
Emulation of 24CXX Serial EPROMs
Available in 3.3V ± 10% LV and 5V Versions
System Friendly READY Pin
Description
The AT17C512/010 and AT17LV512/010 (high-density AT17 Series) FPGA Configu-
ration EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration
memory for Field Programmable Gate Arrays. The high-density AT17 Series is pack-
aged in the popular 20-pin PLCC. The high-density AT17 Series family uses a simple
serial-access procedure to configure one or more FPGA devices. The high-density
AT17 Series organization supplies enough memory to configure one or multiple
smaller FPGAs. The user can select the polarity of the reset function by programming
one EEPROM byte. The devices also support a write protection mode and a system
friendly READY pin, which signifies a “good” power level to the device and can be
used to ensure reliable system power-up.
The high-density AT17 Series can be programmed with industry-standard program-
mers, and the Atmel ATDH2200 Programming board.
FPGA
Configuration
E2PROM
Memory
512K and 1M
AT17C512
AT17LV512
AT17C010
AT17LV010
Pin Configurations
20-Pin PLCC
D
AV
N T NCN
CACCC
3 2 1 20 19
CLK 4
18 NC
WP1 5
17 SER_EN
RESET/OE 6
16 NC
WP2 7
1 5 READY
CE 8
14 CEO
9 10 11 12 13
NGNNN
CNCCC
D
Rev. 0944A-A–12/97
1



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AT17C512 pdf
Controlling The High-Density AT17 Series Serial EEPROMs
Most connections between the FPGA device and the Serial
EEPROM are simple and self-explanatory:
• The DATA output of the high-density AT17 Series drives
DIN of the FPGA devices.
• The master FPGA CCLK output drives the CLK input of
the high-density AT17 Series.
• The CEO output of any AT17C/LV512/010 drives the CE
input of the next AT17C/LV512/010 in a cascade chain of
PROMs.
• SER_EN must be connected to VCC, (except during
ISP).
READY is available as an open-collector indicator of the
device’s RESET status; it is driven Low while the device is
in its POWER-ON RESET cycle and released (tri-stated)
when the cycle is complete.
There are two different ways to use the inputs CE and OE,
as shown in the AC Characteristics waveforms.
Condition 1
The simplest connection is to have the FPGA D/P output
drive both CE and RESET/OE in parallel (Figure 1). Due to
its simplicity, however, this method will fail if the FPGA
receives an external reset condition during the configura-
tion cycle. If a system reset is applied to the FPGA, it will
abort the original configuration and then reset itself for a
new configuration, as intended. Of course, the high-density
AT17 Series does not see the external reset signal and will
not reset its internal address counters and, consequently,
will remain out of sync with the FPGA for the remainder of
the configuration cycle.
Condition 2
The FPGA D/P output drives only the CE input of the high-
density AT17 Series, while its OE input is driven by the
inversion of the input to the FPGA RESET input pin. This
connection works under all normal circumstances, even
when the user aborts a configuration before D/P has gone
High. A High level on the RESET/OE input to the
AT17C/LVxxx – during FPGA reset – clears the Configura-
tor’s internal address pointer, so that the reconfiguration
starts at the beginning. The high-density AT17 Series does
not require an inverter since the RESET polarity is pro-
grammable.
Block Diagram
2 AT17C/LV512/010



Part Number AT17C512
Description FPGA Configuration E2PROM Memory
Maker ATMEL Corporation - ATMEL Corporation
Total Page 9 Pages
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