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FPGA Configuration EEPROM

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AT17C256A pdf
EE Programmable 65,536 x 1, 131,072 x 1 and 262,144 x 1 bit Serial Memories Designed
to Store Configuration Programs for Programmable Gate Arrays
Simple Interface to SRAM FPGAs Requires Only One User I/O Pin
Able to Configure with EPF6000 and EPF8000, Flex 10K FPGAs
Cascadable To Support Additional Configurations or Future Higher-Density Arrays
(17C128/256 only)
Low-Power CMOS EEPROM Process
Programmable Reset Polarity
Available in Industry-Standard Pin-Compatible PLCC Package
In-System Programmable via 2-Wire Bus
Emulation of 24CXX Serial EEPROMs
Available in 3.3V and 5V Versions
The AT17C65/128/256A and AT17LV65/128/256A (AT17A Series) FPGA Configura-
tion EEPROMS (Configurator) provide an easy-to-use, cost-effective configuration
memory for Field Programmable Gate Arrays. The AT17A Series is packaged in the
popular 20-pin PLCC. The AT17A Series family uses a simple serial-access provides
to configure one or more FPGA devices. The AT17A Series organization supplies
enough memory to configure one or multiple smaller FPGAs. Using a special feature
of the AT17A Series, the user can select the polarity of the reset function by program-
ming a special EEPROM bit.
The AT17A Series is pin compatible with the industry standard configurator, and can
be programmed with industry standard programmers.
Pin Configurations
20-Pin PLCC
65K, 128K and 256K
17 NC
16 NC
15 NC
14 NC
Rev. 0996A–07/98

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AT17C256A pdf
Controlling The AT17A Series Serial EEPROMs
Most connections between the FPGA device and the serial
EEPROM are simple and self-explanatory.
• The DATA output of the AT17A Series drives DIN of the
FPGA devices.
• The master FPGA CCLK output drives the CLK input of
the AT17A Series.
• The CEO output of any AT17C/LV128/256A drives the
CE input of the next AT17C/LV65/128/256 in a cascade
chain of PROMs.
• SER_EN must be connected to VCC.
There are, however, two different ways to use the inputs
CE and OE, as shown in the AC Characteristics wave-
Condition 1
The simplest connection is to have the FPGA D/P output
drive both CE and RESET/OE in parallel (Figure 1). Due to
its simplicity, however, this method will fail if the FPGA
receives an external reset condition during the configura-
tion cycle. If a system reset is applied to the FPGA, it will
abort the original configuration and then reset itself for a
new configuration, as intended. Of course, the AT17A
Series does not see the external reset signal and will not
reset its internal address counters and, consequently, will
remain out of sync with the FPGA for the remainder of the
configuration cycle.
Condition 2
The FPGA D/P output drives only the CE input of the
AT17A Series, while its OE input is driven by the inversion
of the input to the FPGA RESET input pin. This connection
works under all normal circumstances, even when the user
aborts a configuration before D/P has gone high. A high
level on the RESET/OE input to the AT17C/LVxxxA – dur-
ing FPGA reset – clears the Configurator's internal address
pointer, so that the reconfiguration starts at the beginning.
The AT17A Series does not require an inverter since the
RESET polarity is programmable.
Block Diagram
2 AT17A Series

Part Number AT17C256A
Description FPGA Configuration EEPROM
Maker ATMEL Corporation - ATMEL Corporation
Total Page 11 Pages
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