Controlling The AT17 Series Serial EEPROMs
Most connections between the FPGA device and the Serial
EEPROM are simple and self-explanatory.
• The DATA output of the AT17 Series drives DIN of the
• The master FPGA CCLK output drives the CLK input of
the AT17 Series.
tion cycle. If a system reset is applied to the FPGA, it will
abort the original configuration and then reset itself for a
new configuration, as intended. Of course, the AT17 Series
does not see the external reset signal and will not reset its
internal address counters and, consequently, will remain
out of sync with the FPGA for the remainder of the configu-
• The CEO output of any AT17C/LV128/256 drives the CE
input of the next AT17C/LV128/256 in a cascade chain of
• SER_EN must be connected to VCC.
There are, however, two different ways to use the inputs
CE and OE, as shown in the AC Characteristics wave-
The simplest connection is to have the FPGA D/P output
drive both CE and RESET/OE in parallel (Figure 1). Due to
its simplicity, however, this method will fail if the FPGA
receives an external reset condition during the configura-
The FPGA D/P output drives only the CE input of the AT17
Series, while its OE input is driven by the inversion of the
input to the FPGA RESET input pin. This connection works
under all normal circumstances, even when the user aborts
a configuration before D/P has gone High. A High level on
the RESET/OE input to the AT17C/LVxxx – during FPGA
reset – clears the Configurator's internal address pointer,
so that the reconfiguration starts at the beginning. The
AT17 Series does not require an inverter since the RESET
polarity is programmable.
2 AT17 Series