Low Offset Voltage Drift
Matched Offset Voltage
Matched Offset Voltage Over Temperature
Matched Bias Currents
Crosstalk: –124 dB at 1 kHz
Low Bias Current: 35 pA max Warmed Up
Low Offset Voltage: 250 V max
Low Input Voltage Noise: 2 V p-p
High Open Loop Gain: 108 dB
Low Quiescent Current: 2.8 mA max
Low Total Harmonic Distortion
Standard Dual Amplifier Pinout
Available in Hermetic Metal Can Package, Hermetic
Surface Mount (20-Pin LCC) and Chip Form
MIL-STD-883B Processing Also Available
Single Version Available: AD547
Dual BiFET Op Amp
The AD647 is an ultralow drift, dual JFET amplifier that com-
bines high performance and convenience in a single package.
The AD647 uses the most advanced ion-implantation and laser
wafer drift trimming technologies to achieve the highest perfor-
mance currently available in a dual JFET. Ion-implantation per-
mits the fabrication of matched JFETs on a monolithic bipolar
chip. Laser wafer drift trimming trims both the initial offset volt-
age and its drift with temperature to provide offsets as low as
100 µV (250 µV max) and drifts of 2.5 µV/°C max.
In addition to outstanding individual amplifier performance, the
AD647 offers guaranteed and tested matching performance on
critical parameters such as offset voltage, offset voltage drift and
The high level of performance makes the AD647 especially well
suited for high precision instrumentation amplifier applications
that previously would have required the costly selection and
matching of space wasting single amplifiers.
The AD647 is offered in four performance grades, three com-
mercial (the J, K and L) and one extended (the S). All are sup-
plied in hermetically sealed 8-pin TO-99 packages and are
available processed to MIL-STD-883B. The LCC version is
also available processed to MIL-STD-883B.
1. The AD647 is guaranteed and tested to tight matching speci-
fications to ensure high performance and to eliminate the se-
lection and matching of single devices.
2. Laser wafer drift trimming reduces offset voltage and offset
voltage drifts to 250 µV and 2.5 µV/°C max.
3. Voltage noise is guaranteed at 4 µV p-p max (0.1 Hz to
10 Hz) on K, L and S grades.
4. Bias current (35 pA K, L, S; 75 pA J) is specified after five
minutes of operation.
5. Total supply current is a low 2.8 mA max.
6. High open loop gain ensures high linearity in precision instru-
mentation amplifier applications.
7. The standard dual amplifier pinout permits the direct substi-
tution of the AD647 for lower performance devices.
8. The AD647 is available in chip form.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
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