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Analog Devices Semiconductor Electronic Components Datasheet



AD1958

PLL/Multibit DAC


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AD1958 pdf
a
PLL/Multibit -DAC
AD1958
FEATURES
5 V Stereo Audio DAC System
Accepts 16-/18-/20-/24-Bit Data
Supports 24 Bits, 192 kHz Sample Rate
Accepts a Wide Range of Sample Rates Including:
32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz
Multibit Sigma-Delta Modulator with “Perfect Differential
Linearity Restoration” for Reduced Idle Tones and
Noise Floor
Data Directed Scrambling DAC—Least Sensitive to Jitter
Single-Ended Output for Easy Use
108 dB Signal-to-Noise (Not Muted) at 48 kHz Sample
Rate (A-Weighted Stereo)
109 dB Dynamic Range (Not Muted) at 48 kHz Sample
Rate (A-Weighted Stereo)
–96 dB THD + N (Stereo)
75 dB Stop Band Attenuation
On-Chip Clickless Volume Control
Hardware and Software Controllable Clickless Mute
Serial (SPI) Control for: Serial Mode, Number of Bits,
Sample Rate, Volume, Mute, De-Emphasis
Digital De-Emphasis Processing for 32 kHz, 44.1 kHz,
and 48 kHz Sample Rates
Programmable Dual Fractional-N PLL Clock Generator
27 MHz Master Clock Oscillator
Better than 100 ps rms Master Clock Jitter
Generated System Clocks
SCLK0: 33.8688 MHz
SCLK1: 22.5792 MHz, 24.576 MHz, 33.8688 MHz, or
36.864 MHz
SCLK2: 16.9344 MHz
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S-Compatible, and DSP Serial Port Modes
28-Lead SSOP Plastic Package
APPLICATIONS
DVD, CD, Home Theater Systems, Automotive Audio
Systems, Sampling Musical Keyboards, Digital Mixing
Consoles, Digital Audio Effects Processors
PRODUCT OVERVIEW
The AD1958 is a complete high-performance single-chip stereo
digital audio playback system. It is comprised of a multibit sigma-
delta modulator, digital interpolation filters, and analog output
drive circuitry with an on-board dual PLL clock generator.
Other features include an on-chip stereo attenuator and mute,
programmed through an SPI-compatible serial control port.
The AD1958 is fully compatible with all known DVD formats
including 96 kHz and 192 kHz sample frequencies and 24 bits.
It also is backwards-compatible by supporting 50 µs/15 µs
digital de-emphasis for “redbook” compact discs, as well as
de-emphasis at 32 kHz and 48 kHz sample rates.
The AD1958 has a simple but flexible serial data input port that
allows for glueless interconnection to a variety of ADCs, DSP
chips, AES/EBU receivers, and sample rate converters. The
AD1958 can be configured in left-justified, I2S, right-justified,
or DSP serial-port-compatible modes. It can support 16, 20,
and 24 bits in all modes. The AD1958 accepts serial audio data
in MSB first, two’s-complement format, and operates from a
single 5 V power supply. It is fabricated on a single monolithic
integrated circuit and housed in a 28-lead SSOP package for
operation over the temperature range –40°C to +105°C.
FUNCTIONAL BLOCK DIAGRAM
XIN XOUT MCLK
LOOP CLOCK
FILTERS OUTPUTS
23
CONTROL DATA
INPUT
3
AD1958
OSC
PLL
CIRCUIT
SERIAL CONTROL
INTERFACE
VOLTAGE
REFERENCE
16-/20-/24-
BIT DIGITAL
DATA INPUT
3
SERIAL
DATA
INTERFACE
ATTEN/MUTE
ATTEN/MUTE
8 ؋ fS
INTERPOLATOR
8 ؋ fS
INTERPOLATOR
MULTIBIT
SIGMA-DELTA
MODULATOR
MULTIBIT
SIGMA-DELTA
MODULATOR
DAC
DAC
OUTPUT
BUFFER
OUTPUT
BUFFER
L
ANALOG
OUTPUTS
R
REV. 0
RESET MUTE ZERO FLAG
2
PLL SUPPLY
2
DIGITAL SUPPLY
3
ANALOG SUPPLY
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001



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AD1958 pdf
AD1958–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages
(AVDD, DVDD, PVDD)
5.0 V
Ambient Temperature
25°C
Input Clock
Input Signal
12.288 MHz (256 × fS Mode)
996.0938 Hz,
0 dB Full Scale
Input Sample Rate
48 kHz
Measurement Bandwidth
20 Hz to 20 kHz
Word Width
24 Bits
Load Capacitance
100 pF
Load Impedance
47 k
Input Voltage HI
2.0 V
Input Voltage LO
0.8 V
ANALOG PERFORMANCE
Min Typ Max
Resolution
Signal-to-Noise Ratio (20 Hz to 20 kHz)
No Filter (Stereo)
With A-Weighted Filter (Stereo)
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
No Filter (Stereo)
With A-Weighted Filter (Stereo)
Total Harmonic Distortion + Noise (Stereo)
PLL Performance
Master Clock Input Frequency
Generated System Clocks
SCLK0
SCLK1
SCLK2
Jitter (SCLK0 and SCLK1)
Jitter (MCLK)
Duty Cycle (SCLK0, SCLK1)1
Duty Cycle (MCLK)
Analog Outputs
Single-Ended Output Range (± Full Scale)
Output Capacitance at Each Output Pin
Out-of-Band Energy (0.5 × fS to 100 kHz)
VREF (FILTR)
DC Accuracy
Gain Error
Interchannel Gain Mismatch
Gain Drift
DC Offset
Interchannel Crosstalk (EIAJ Method)
Interchannel Phase Deviation
Mute Attenuation
De-Emphasis Gain Error
102
–90
49
–5
–0.15
–25
24
105
108
105
109
–96
27
33.8688
12.288
22.5792
110
60
50
50
3.17
2.39
± 2.0
± 0.015
150
–3
–120
± 0.1
–100
175
100
51
2
–90
+5
+0.15
250
+20
± 0.1
NOTES
1In some combinations with Clock Configuration Mode = 1 (see Table III), SCLK will not be 50%.
2Performance of right and left channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.
DIGITAL I/O (–40°C to +105°C )
Min Typ Max
Input Voltage HI (VIH)
Input Voltage LO (VIL)
Input Leakage (IIH @ VIH = 2.4 V)
Input Leakage (IIL @ VIL = 0.8 V)
High Level Output Voltage (VOH) IOH = 1 mA
Low Level Output Voltage (VOL) IOL = 1 mA
Input Capacitance
2.0
3.5
0.8
10
10
0.4
20
Specifications subject to change without notice.
–2–
Unit
Bits
dB
dB
dB
dB
dB
MHz
MHz
MHz
MHz
ps rms
ps rms
%
%
V p-p
pF
dB
V
%
dB
ppm/°C
mV
dB
Degrees
dB
dB
Unit
V
V
µA
µA
V
V
pF
REV. 0



Part Number AD1958
Description PLL/Multibit DAC
Maker Analog Devices - Analog Devices
Total Page 8 Pages
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