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Analog Devices Semiconductor Electronic Components Datasheet



AD1892

Integrated Digital Receiver/Rate Converter


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AD1892 pdf
a
Integrated Digital
Receiver/Rate Converter
AD1892
FEATURES
Complete EIAJ CP-340 (CP-1201), IEC-958, AES/EBU,
S/PDIF Compatible Digital Audio Receiver and
Asynchronous Sample Rate Converter
Status Pins and Microprocessor Interfaces for
Stand-Alone and Microcontroller-Oriented Operation
Integrated Channel Status Buffer and Q-Channel
Subcode Buffer (Supports EIAJ CP-2401)
20-Bit SamplePort® Architecture Provides Superb Jitter
Rejection on Input Port
Sample Rate Conversion from 8 kHz to 48 kHz with
1:5 Upsampling Range
1:0.85 Downsampling Range
120 dB Dynamic Range
–113 dB THD+N @ 1 kHz
CRC Calculation on Q-Channel Subcode (Consumer
Mode Only) and on Channel Status (Pro Mode Only)
Four-Wire SPI™ Compatible Serial Control Port
Mute Input Pin
Power-Down Mode
Single +5 V Supply
Flexible Three-Wire Serial Data Port with Left-Justified,
Right-Justified and I2S-Compatible Modes
28-Lead SOIC Package
APPLICATIONS
DVD, DAT, MD, DCC and CD-R Recorders and Players
Computer Multimedia Products
DAB Receivers, Automotive Digital Audio Networks
PRODUCT OVERVIEW
The AD1892 combines a CP-1201, CP-340, IEC-958, AES/
EBU, S/PDIF compatible Digital Audio Receiver (DAR) with
an asynchronous sample rate converter, allowing the user to
specify the output sample rate of the received digital audio infor-
mation. The DAR block features support for both Q-channel
subcode information (to support CD, CD-R, MD and DAT
digital audio formats) as well as Channel Status information. A
microcontroller interface, with an SPI compatible serial port,
allows full access to the 80-bit Q-Channel subcode buffer and to
the 32-bit Channel Status buffer, as well as to the control and
status registers. Additionally, key status information from the
incoming subframes and the Channel Status buffer is reported
on status output pins on the AD1892, so the AD1892 may be
used in systems that do not include a microcontroller or
microprocessor.
The asynchronous sample rate converter block is based on
market leading AD1890 family SamplePort rate conversion tech-
nology. The AD1892 offers a 1:5 upsampling range, and will
downsample from 48 kHz to 44.1 kHz. Input audio word widths
up to 20 bits are supported, and output audio word widths of 16
or 20 are supported, with 120 dB of dynamic range and –113 dB
THD+N. The rate converter inherently rejects jitter on the
recovered clocks from the incoming biphase-mark encoded
stream. Indeed, sample rate conversion is highly synergistic
with digital audio reception, allowing the use of a fully digital
phase locked loop clock recovery scheme with highly robust
clock recovery and jitter rejection.
(continued on Page 4)
FUNCTIONAL BLOCK DIAGRAM
512 x FSOUT
POWER-DOWN/RESET
MUTE
BIPHASE-MARK 2
INPUT
CLOCK
GENERATOR
ASYNCH SAMPLE
RATE CONVERTER
OUTPUT SERIAL
INTERFACE
BIPHASE-MARK
RECEIVER
COMPARATOR
DATA
BYPASS
CONTROL
AD1892
CRC
Q-CHANNEL
CHECK SUBCODE BUFFER
CRC CHANNEL STATUS
CHECK
BUFFER
MICROCONTROLLER
INTERFACE
3 BCLK
LRCLK
SDATA
SYNC
CA
CB
CC
CD
CE
CON/PRO
CSCLK
NO ERROR INTERRUPT U/C BIT SFCLK QDFS
SIGNAL
4
CLOCK, LATCH,
DATA IN,
DATA OUT
2
DIGITAL
SUPPLY
SamplePort is a registered trademark of Analog Devices, Inc.
SPI is a trademark of Motorola, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998



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AD1892 pdf
AD1892–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltage
+5.0 V
Ambient Temperature
25 °C
Output Sample Frequency (FSOUT)
MCLK
Input Word Width
48.8
25
20
kHz
MHz (512 × FSOUT)
Bits
Load Capacitance
100 pF
All minimums and maximums tested except as noted.
PERFORMANCE1
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
Total Harmonic Distortion + Noise
(20 Hz to 20 kHz, Full-Scale Input)
(1 kHz Full-Scale Input)
(10 kHz Full-Scale Input)
Interchannel Phase Deviation
DIGITAL I/O1
VIH
VIL
IIH @ VIH = +5.0 V
IIL @ VIL = 0 V
VOH @ IOH = –0.5 mA
VOL @ IOL = 0.5 mA
Input Capacitance1
DIGITAL TIMING1
tMCP
FMCLK
tPDRP
tBDM
tLDM
tDDP
tDDS
tDDH
tSSU
tCCH
tCCL
tCCP
tCSU
tCHD
tCOH
tSFPW
tSFSU
tCSPW
tQDH
tCLH
tCLK
tRS
MCLK Duty Cycle1
MCLK Frequency (1/tMCP)1
PD/RST LO Pulsewidth
BCLK Propagation Delay from MCLK (to Falling Edge)
LRCLK Propagation Delay from MCLK
Data Propagation Delay from MCLK
Data Output Setup to BCLK
Data Output Hold from BCLK
SYNC Falling Setup to MCLK Rising
CCLK HI Pulsewidth
CCLK LO Pulsewidth
CCLK Period
SDI Setup
SDI Hold
SDO Propagation Delay from CCLK
SFCLK HI Pulsewidth1
U/CBIT, INT, ERROR Setup to SFCLK
CSCLK HI Pulsewidth1
QDFS HI Pulsewidth1
CS HI Pulsewidth
CS Falling Edge to CCLK Rising
PD/RST Rising to MCLK Rising Edge (Only Required
for Synchronizing Multiple Parts)
DIGITAL RS-422 RECEIVERS (RXP, RXN Pins Only)
Input Resistance
Min Differential AES/EBU or S/PDIF Input
Input Hysteresis
–2–
Min Typ Max
120
–103
–113
–107
0
Min Typ
2.4
DVDD – (0.5)
15
Max
0.8
10
10
0.5
Min Typ
40
10 × MCLK Period
1/2 BCLK Period
1/2 BCLK Period
5
20
20
8 × MCLK Period
15
10
100
100
100
1000
10 × MCLK Period
3 × MCLK Period
5
Max
60
25
30
30
30
30
Min Typ Max
20
200
20
Units
dB
dB
dB
dB
Degrees
Units
V
V
µA
µA
V
V
pF
Units
%
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
k
mV p-p
mV
REV. 0



Part Number AD1892
Description Integrated Digital Receiver/Rate Converter
Maker Analog Devices - Analog Devices
Total Page 24 Pages
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