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Analog Devices Semiconductor Electronic Components Datasheet



AD1891

SamplePort Stereo Asynchronous Sample Rate Converters



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AD1891 pdf
a
SamplePort Stereo Asynchronous
Sample Rate Converters
AD1890/AD1891
FEATURES
Automatically Sense Sample Frequencies—No
Programming Required
Tolerant of Sample Clock Jitter
Smooth Transition When Sample Clock Frequencies
Cross
Accommodate Dynamically Changing Asynchronous
Sample Clocks
8 kHz to 56 kHz Sample Clock Frequency Range
1:2 to 2:1 Ratio Between Sample Clocks
–106 dB THD+N at 1 kHz (AD1890)
120 dB Dynamic Range (AD1890)
Optimal Clock Tracking Control
–Short/Long Group Delay Modes
–Slow/Fast Settling Modes
Linear Phase in All Modes
Equivalent of 4 Million 22-Bit FIR Filter Coefficients
Stored On-Chip
Automatic Output Mute
Flexible Four Wire Serial Interfaces
Low Power
APPLICATIONS
Digital Mixing Consoles and Digital Audio Workstations
CD-R, DAT, DCC and MD Recorders
Multitrack Digital Audio and Video Tape Recorders
Studio to Transmitter Links
Digital Audio Signal Routers/Switches
Digital Audio Broadcast Equipment
High Quality D/A Converters
Digital Tape Recorder Varispeed Applications
Computer Communication and Multimedia Systems
PRODUCT OVERVIEW
The AD1890 and AD1891 SamplePorts™ are fully digital, stereo
Asynchronous Sample Rate Converters (ASRCs) that solve sample
rate interfacing and compatibility problems in digital audio equip-
ment. Conceptually, these converters interpolate the input data up
to a very high internal sample rate with a time resolution of 300 ps,
then decimate down to the desired output sample rate. The
AD1890 is intended for 18- and 20-bit professional applications,
and the AD1891 is intended for 16-bit lower cost applications
where large dynamic sample-rate changes are not encountered.
These devices are asynchronous because the frequency and phase
relationships between the input and output sample clocks (both are
inputs to the AD1890/AD1891 ASRCs) are arbitrary and need not
be related by a simple integer ratio. There is no need to explicitly
select or program the input and output sample clock frequencies, as
the AD1890/AD1891 automatically sense the relationship between
SamplePort and SamplePorts are trademarks of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
SYSTEM DIAGRAM
EXAMPLE
FREQUENCIES:
DAT 48kHz OR
CD 44.1kHz OR
BROADCAST 32kHz
INPUT SAMPLE CLOCK
AD1890/
AD1891
EXAMPLE
FREQUENCIES:
DAT 48kHz OR
CD 44.1kHz OR
BROADCAST 32kHz
OUTPUT SAMPLE CLOCK
INPUT SERIAL DATA
OUTPUT SERIAL DATA
the two clocks. The input and output sample clock frequencies
can nominally range from 8 kHz to 56 kHz, and the ratio
between them can vary from 1:2 to 2:1.
The AD1890/AD1891 use multirate digital signal processing
techniques to construct an output sample stream from the input
sample stream. The input word width is 4 to 20 bits for the
AD1890 or 4 to 16 bits for the AD1891. Shorter input words
are automatically zero-filled in the LSBs. The output word
width for both devices is 24 bits. The user can receive as many
of the output bits as desired. Internal arithmetic is performed
with 22-bit coefficients and 27-bit accumulation. The digital
samples are processed with unity gain.
The input and output control signals allow for considerable flex-
ibility for interfacing to a variety of DSP chips, AES/EBU
receivers and transmitters and for I2S compatible devices. Input
and output data can be independently justified to the left/right
clock edge, or delayed by one bit clock from the left/right clock
edge. Input and output data can also be independently justified
to the word clock rising edge or delayed by one bit clock from
the word clock rising edge. The bit clocks can also be indepen-
dently configured for rising edge active or falling edge active
operation.
The AD1890/AD1891 SamplePort™ ASRCs have on-chip digi-
tal coefficients that correspond to a highly oversampled 0 kHz to
20 kHz low-pass filter with a flat passband, a very narrow tran-
sition band, and a high degree of stopband attenuation. A subset
of these filter coefficients are dynamically chosen on the basis of
the filtered instantaneous ratio between the input sample clock
(LR_I) and the output sample clock (LR_O), and these coeffi-
cients are used in an FIR convolver to perform the sample rate
conversion. Refer to the “Theory of Operation” section of this
data sheet for a more thorough functional description. The low-
pass filter has been designed so that full 20 kHz bandwidth is
maintained when the input and output sample clock frequencies
are as low as 44.1 kHz. If the output sample rate drops below
the input sample rate, the bandwidth of the input signal is
(continued on Page 4)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703



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AD1891 pdf
AD1890/AD1891–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltage
Ambient Temperature
MCLK
Load Capacitance
+5.0
25
20
100
V
°C
MHz
pF
All minimums and maximums tested except as noted.
PERFORMANCE (Guaranteed over 0°C TA 70°C, VDD = 5.0 V ± 10%, 8 MHz MCLK 20 MHz)
Min
AD1890 Dynamic Range (20 Hz to 20 kHz, –60 dB Input)†
AD1891 Dynamic Range (20 Hz to 20 kHz, –60 dB Input)†
Total Harmonic Distortion + Noise†
AD1890 and AD1891 (20 Hz to 20 kHz, Full-Scale Input,
FSOUT/FSIN Between 0.5 and 2.0)
AD1890 (1 kHz Full-Scale Input, FSOUT/FSIN Between 0.7 and 1.4)
AD1890 (10 kHz Full-Scale Input, FSOUT/FSIN Between 0.7 and 1.4)
AD1891 (1 kHz Full-Scale Input, FSOUT/FSIN Between 0.7 and 1.4)
AD1891 (10 kHz Full-Scale Input, FSOUT/FSIN Between 0.7 and 1.4)
Interchannel Phase Deviation†
Input and Output Sample Clock Jitter†
(For 1 dB Degradation in THD+N with 10 kHz Full-Scale Input, Slow-Settling Mode)
120
96
10
DIGITAL INPUTS (Guaranteed over 0°C TA 70°C, VDD = 5.0 V ± 10%, 8 MHz MCLK 20 MHz)
Min
VIH
VIL
IIH @ VIH = +5 V
IIL @ VIL = 0 V
VOH @ IOH = –4 mA
VOL @ IOL = 4 mA
Input Capacitance†
2.2
3.6
DIGITAL TIMING (Guaranteed over 0°C TA 70°C, VDD = 5.0 V ± 10%, 8 MHz MCLK 20 MHz)
Min
tMCLK
fMCLK
tMPWL
tMPWH
fLRI
tRPWL
tRS
tBCLK
fBCLK
tBPWL
tBPWH
tWSI
tWSO
tLRSI
tLRSO
tDS
tDH
tDPD
tDOH
MCLK Period
MCLK Frequency (1/tMCLK)
MCLK LO Pulse Width
MCLK HI Pulse Width
LR_I Frequency with 20 MHz MCLK†
RESET LO Pulse Width
RESET Setup to MCLK Falling
BCLK_I/O Period†
BCLK_I/O Frequency (l/tBCLK)†
BCLK_I/O LO Pulse Width
BCLK_I/O HI Pulse Width
WCLK_I Setup to BCLK_I
WCLK_O Setup to BCLK_O
LR_I Setup to BCLK_I
LR_O Setup to BCLK_O
Data Setup to BCLK_I
Data Hold from BCLK_I
Data Propagation Delay from BCLK_O
Data Output Hold from BCLK_O
50
8
20
20
10
100
15
80
40
40
15
30
15
30
0
25
5
Max
–94
–106
–100
–96
–95
0
Max
0. 8
4
4
0.4
15
Max
125
20
70
12.5
40
Units
dB
dB
dB
dB
dB
dB
dB
dB
Degrees
ns
Units
V
V
µA
µA
V
V
pF
Units
ns
MHz
ns
ns
kHz
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2– REV. 0



Part Number AD1891
Description SamplePort Stereo Asynchronous Sample Rate Converters
Maker Analog Devices - Analog Devices
Total Page 20 Pages
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