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Analog Devices Semiconductor Electronic Components Datasheet



AD1877

Single-Supply 16-Bit Stereo ADC


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AD1877 pdf
a
Single-Supply
16-Bit ⌺⌬ Stereo ADC
AD1877*
FEATURES
Single 5 V Power Supply
Single-Ended Dual-Channel Analog Inputs
92 dB (Typ) Dynamic Range
90 dB (Typ) S/(THD+N)
0.006 dB Decimator Passband Ripple
Fourth-Order, 64-Times Oversampling ⌺⌬ Modulator
Three-Stage, Linear-Phase Decimator
256 ؋ FS or 384 ؋ FS Input Clock
Less than 100 W (Typ) Power-Down Mode
Input Overrange Indication
On-Chip Voltage Reference
Flexible Serial Output Interface
28-Lead SOIC Package
APPLICATIONS
Consumer Digital Audio Receivers
Digital Audio Recorders, Including Portables
CD-R, DCC, MD and DAT
Multimedia and Consumer Electronic Equipment
Sampling Music Synthesizers
Digital Karaoke Systems
PRODUCT OVERVIEW
The AD1877 is a stereo, 16-bit oversampling ADC based on
Sigma Delta (∑∆) technology intended primarily for digital
audio bandwidth applications requiring a single 5 V power supply.
Each single-ended channel consists of a fourth-order one-bit
noise shaping modulator and a digital decimation filter. An on-
chip voltage reference, stable over temperature and time, defines
the full-scale range for both channels. Digital output data from
both channels are time-multiplexed to a single, flexible serial
interface. The AD1877 accepts a 256 × FS or a 384 × FS input
clock (FS is the sampling frequency) and operates in both serial
port “master” and “slave” modes. In slave mode, all clocks must
be externally derived from a common source.
Input signals are sampled at 64 × FS onto internally buffered
switched-capacitors, eliminating external sample-and-hold ampli-
fiers and minimizing the requirements for antialias filtering at the
input. With simplified antialiasing, linear phase can be preserved
across the passband. The on-chip single-ended to differential signal
converters save the board designer from having to provide them
externally. The AD1877’s internal differential architecture provides
increased dynamic range and excellent power supply rejection
characteristics. The AD1877’s proprietary fourth-order differen-
tial switched-capacitor ∑∆ modulator architecture shapes the
*Protected by U.S. Patent Numbers 5055843, 5126653, and others pending.
FUNCTIONAL BLOCK DIAGRAM
LRCK 1
WCLK 2
BCLK 3
DVDD1 4
DGND1 5
RDEDGE 6
S/M 7
384/256 8
AVDD 9
VINL 10
CAPL1 11
CAPL2 12
AGNDL 13
VREFL 14
SERIAL OUTPUT
INTERFACE
CLOCK
DIVIDER
THREE-STAGE FIR
DECIMATION
FILTER
THREE-STAGE FIR
DECIMATION
FILTER
D DD D
A AA A
C CC C
SINGLE TO
SINGLE TO
DIFFERENTIAL INPUT DIFFERENTIAL INPUT
CONVERTER
CONVERTER
VOLTAGE
REFERENCE
AD1877
28 CLKIN
27 TAG
26 SOUT
25 DVDD2
24 DGND2
23 RESET
22 MSBDLY
21 RLJUST
20 AGND
19 VINR
18 CAPR1
17 CAPR2
16 AGNDR
15 VREFR
one-bit comparator’s quantization noise out of the audio pass-
band. The high order of the modulator randomizes the modulator
output, reducing idle tones in the AD1877 to very low levels.
Because its modulator is single-bit, AD1877 is inherently
monotonic and has no mechanism for producing differential
linearity errors.
The input section of the AD1877 uses autocalibration to correct
any dc offset voltage present in the circuit, provided that the inputs
are ac coupled. The single-ended dc input voltage can swing
between 0.7 V and 3.8 V typically. The AD1877 antialias input
circuit requires four external 470 pF NPO ceramic chip filter
capacitors, two for each channel. No active electronics are
needed. Decoupling capacitors for the supply and reference pins
are also required.
The dual digital decimation filters are triple-stage, finite impulse
response filters for effectively removing the modulator’s high
frequency quantization noise and reducing the 64 × FS single-bit
output data rate to an FS word rate. They provide linear phase
and a narrow transition band that properly digitizes 20 kHz signals
at a 44.1 kHz sampling frequency. Passband ripple is less than
0.006 dB, and stopband attenuation exceeds 90 dB.
(Continued on Page 6)
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000



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AD1877 pdf
AD1877–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages
5.0 V
Ambient Temperature
25 °C
Input Clock (FCLKIN) [256 × FS]
Input Signal
12.288
991.768
MHz
Hz
–0.5 dB Full Scale
Measurement Bandwidth
23.2 Hz to 19.998 kHz
Load Capacitance on Digital Outputs 50
pF
Input Voltage HI (VIH)
2.4 V
Input Voltage LO (VIL)
0.8 V
Master Mode, Data I2S-Justified (Refer to Figure 14).
Device Under Test (DUT) bypassed and decoupled as shown in Figure 3.
DUT is antialiased and ac coupled as shown in Figure 2. DUT is calibrated.
Values in bold typeface are tested, all others are guaranteed but not tested.
ANALOG PERFORMANCE
Resolution
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
Without A-Weight Filter
With A-Weight Filter
Signal to (THD + Noise)
Signal to THD
Analog Inputs
Single-Ended Input Range (± Full Scale)*
Input Impedance at Each Input Pin
VREF
DC Accuracy
Gain Error
Interchannel Gain Mismatch
Gain Drift
Midscale Offset Error (After Calibration)
Midscale Drift
Crosstalk (EIAJ Method)
*VIN p-p = VREF × 1.333.
Min
87
90
86.5
92
VREF – 1.55
2.05
–90
Typ
16
92
94
90
94
VREF
32
2.25
± 0.5
0.01
115
±3
15
–99
Max
VREF + 1.55
2.55
؎2.5
؎20
Unit
Bits
dB
dB
dB
dB
V
k
V
%
dB
ppm/°C
LSBs
ppm/°C
dB
–2– REV. A



Part Number AD1877
Description Single-Supply 16-Bit Stereo ADC
Maker Analog Devices - Analog Devices
Total Page 18 Pages
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