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Analog Devices Semiconductor Electronic Components Datasheet



AD14160

Quad-SHARC DSP Multiprocessor Family


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AD14160 pdf
a
PERFORMANCE FEATURES
ADSP-21060 Core Processor (. . . ؋4)
480 MFLOPS Peak, 320 MFLOPS Sustained
25 ns Instruction Rate, Single-Cycle
Instruction Execution–Each of Four Processors
16 Mbit Shared SRAM (Internal to SHARCs)
4 Gigawords Addressable Off-Module Memory
Sixteen 40 Mbyte/s Link Ports (Four per SHARC)
Eight 40 Mbit/s Independent Serial Ports (Two
from Each SHARC)
5 V and 3.3 V Operation
32-Bit Single Precision and 40-Bit Extended
Precision IEEE Floating Point Data Formats, or
32-Bit Fixed Point Data Format
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation
PACKAGING FEATURES
452-Lead Ceramic Ball Grid Array (CBGA)
1.85" (47 mm) Body Size
0.200" Max Height
0.050" Ball Pitch
29 Grams (typical)
JC = 0.36؇C/W
Quad-SHARC®
DSP Multiprocessor Family
AD14160/AD14160L
FUNCTIONAL BLOCK DIAGRAM
ID2-0
CPA
SPORT 1
SPORT 0
TDI
SHARC_A
LINK 0
LINK 5
TDO
LINK 0
LINK 5
TDI
SHARC_B
ID2-0
CPA
SPORT 1
SPORT 0
AD14160/
AD14160L
SHARC BUS (ADDR31-0, DATA47-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK,
SBTS, HBR, HBG, REDY, BR6-1, RPBA, DMAR1.2, DMAG1.2)
ID2-0
CPA SHARC_D
SPORT 1
SPORT 0
TDO
LINK 0
LINK 5
TDI
LINK 0 SHARC_C
LINK 5
TDO
ID2-0
CPA
SPORT 1
SPORT 0
GENERAL DESCRIPTION
The AD14160/AD14160L Quad-SHARC Ceramic Ball Grid
Array (CBGA) puts the power of the first generation AD14060
(CQFP) DSP multiprocessor into a very high density ball grid
array package; now with additional link and serial I/O pinned
out, beyond that from the CQFP package. The core of the multi-
processor is the ADSP-21060 DSP microcomputer. The AD14x60
modules have the highest performance—density and lowest
cost— performance ratios of any in their class. They are ideal
for applications requiring higher levels of performance and/or
functionality per unit area.
The AD14160/AD14160L takes advantage of the built-in
multiprocessing features of the ADSP-21060 to achieve 480 peak
MFLOPS with a single chip type, in a single package. The on-
chip SRAM of the DSPs provides 16 Mbits of on-module
shared SRAM. The complete shared bus (48 data, 32 address)
is also brought off-module for interfacing with expansion
memory or other peripherals.
SHARC is a registered trademark of Analog Devices, Inc.
The ADSP-21060 link ports are interconnected to provide
direct communication among the four SHARCs as well as high
speed off-module access. Internally, links connect the SHARC
in a ring. Externally, each SHARC has a total of 160 Mbytes/s
link port bandwidth.
Multiprocessor performance is enhanced with embedded power
and ground planes, matched impedance interconnect, and opti-
mized signal routing lengths and separation. The fully tested
and ready-to-insert multiprocessor also significantly reduces
board space.
s
s
s
s
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998



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AD14160 pdf
AD14160/AD14160L
DETAILED DESCRIPTION
Architectural Features
ADSP-21060 Core
The AD14160/AD14160L is based on the powerful ADSP-21060
(SHARC) DSP chip. The ADSP-21060 SHARC combines a
high performance floating-point DSP core with integrated, on-
chip system features including a 4 Mbit SRAM memory, host
processor interface, DMA controller, serial ports, and both link
port and parallel bus connectivity for glueless DSP multiprocess-
ing, (see Figure 1). It is fabricated in a high speed, low power
CMOS process, and has a 25 ns instruction cycle time. The arith-
metic/ logic unit (ALU), multiplier and shifter all perform single-
cycle instructions, and the three units are arranged in parallel,
maximizing computational throughput.
The SHARC features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data, and the pro-
gram memory (PM) bus transfers both instructions and data.
There is also an on-chip instruction cache which selectively
caches only those instructions whose fetches conflict with the
PM bus data accesses. This combines with the separate program
and data memory buses to enable three-bus operation for fetch-
ing an instruction and two operands, all in a single cycle. The
SHARC also contains a general purpose data register file, which
is a 10-port, 32-register (16 primary, 16 secondary) file. Each
SHARC’s core also implements two data address generators
(DAGs), implementing circular data buffers in hardware. The
DAGs contain sufficient registers to allow the creation of up to
32 circular buffers. The 48-bit instruction word accommodates a
variety of parallel operations, for concise programming. For ex-
ample, the ADSP-21060 can conditionally execute a multiply, an
add, a subtract, and a branch, all in a single instruction.
The SHARCs contain 4 Mbits of on-chip SRAM each, orga-
nized as two blocks of 2 Mbits, which can be configured for
different combinations of code and data storage. The memory
can be configured as a maximum of 128K words of 32-bit data,
256K words of 16-bit data, 80K words of 48-bit instructions (or
40-bit data), or combinations of different word sizes up to
4 megabits. A 16-bit floating-point storage format is supported
which effectively doubles the amount of data that may be stored
on chip. Conversion between the 32-bit floating point and 16-
bit floating point formats is done in a single instruction. Each
memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor or DMA con-
troller. The dual-ported memory and separate on-chip buses
allow two data transfers from the core and one from I/O, all in a
single cycle.
CORE PROCESSOR
TIMER INSTRUCTION
CACHE
32 x 48-BIT
DAG1 DAG2
8 x 4 x 32 8 x 4 x 24
PROGRAM
SEQUENCER
PM ADDRESS BUS
24
DM ADDRESS BUS 32
BUS
CONNECT
(PX)
PM DATA BUS 48
DM DATA BUS 40/32
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
ADDR
DATA
ADDR
DATA
I/O PORT
DATA
ADDR
DATA
ADDR
IOD IOA
48 17
JTAG
TEST AND
EMULATION
7
EXTERNAL
PORT
ADDR BUS
MUX
32
MULTIPROCESSOR
INTERFACE
DATA BUS
MUX
48
HOST PORT
MULTIPLIER
DATA
REGISTER
FILE
16 x 40-BIT
BARREL
SHIFTER
ALU
IOP
REGISTERS
(MEMORY MAPPED)
CONTROL,
STATUS, AND
DATA BUFFERS
DMA
CONTROLLER
SERIAL PORTS
(2)
LINK PORTS
(6)
4
6
6
36
I/O PROCESSOR
Figure 1. ADSP-21060 Processor Block Diagram (Core of the AD14160/AD14160L)
–2– REV. A



Part Number AD14160
Description Quad-SHARC DSP Multiprocessor Family
Maker Analog Devices - Analog Devices
Total Page 52 Pages
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