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National Semiconductor Electronic Components Datasheet


74F175SJ

Quad D Flip-Flop



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74F175SJ pdf
November 1994
54F 74F175 Quad D Flip-Flop
General Description
The ’F175 is a high-speed quad D flip-flop The device is
useful for general flip-flop requirements where clock and
clear inputs are common The information on the D inputs is
stored during the LOW-to-HIGH clock transition Both true
and complemented outputs of each flip-flop are provided A
Master Reset input resets all flip-flops independent of the
Clock or D inputs LOW
Features
Y Edge-triggered D-type inputs
Y Buffered positive edge-triggered clock
Y Asynchronous common reset
Y True and complement output
Y Guaranteed 4000V minimum ESD protection
Commercial
74F175PC
74F175SC (Note 1)
74F175SJ (Note 1)
Military
54F175DM (Note 2)
54F175FM (Note 2)
54F175LM (Note 2)
Package
Number
N16E
J16A
M16A
M16D
W16A
E20A
Package Description
16-Lead (0 300 Wide) Molded Dual-In-Line
16-Lead Ceramic Dual-In-Line
16-Lead (0 150 Wide) Molded Small Outline JEDEC
16-Lead (0 300 Wide) Molded Small Outline EIAJ
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbols
Connection Diagrams
IEEE IEC
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9490–5
TL F 9490 – 1
TL F 9490 – 2
TL F 9490 – 3
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9490
RRD-B30M75 Printed in U S A



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74F175SJ pdf
Unit Loading Fan Out
Pin Names
D0 – D3
CP
MR
Q0 – Q3
Q0 – Q3
Description
Data Inputs
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active LOW)
True Outputs
Complement Outputs
54F 74F
UL
HIGH LOW
10 10
10 10
10 10
50 33 3
50 33 3
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b1 mA 20 mA
b1 mA 20 mA
Functional Description
The ’F175 consists of four edge-triggered D flip-flops with
individual D inputs and Q and Q outputs The Clock and
Master Reset are common The four flip-flops will store the
state of their individual D inputs on the LOW-to-HIGH clock
(CP) transition causing individual Q and Q outputs to follow
A LOW input on the Master Reset (MR) will force all Q out-
puts LOW and Q outputs HIGH independent of Clock or
Data inputs The ’F175 is useful for general logic applica-
tions where a common Master Reset and Clock are accept-
able
Truth Table
Inputs
MR CP Dn
L XX
H LH
H LL
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
L e LOW-to-HIGH Clock Transition
Logic Diagram
Outputs
Qn Qn
LH
HL
LH
TL F 9490 – 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2



Part Number 74F175SJ
Description Quad D Flip-Flop
Maker National Semiconductor - National Semiconductor
Total Page 8 Pages
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