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National Semiconductor Electronic Components Datasheet


74F174SJ

Hex D Flip-Flop with Master Reset


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74F174SJ pdf
November 1994
54F 74F174 Hex D Flip-Flop with Master Reset
General Description
The ’F174 is a high-speed hex D flip-flop The device is
used primarily as a 6-bit edge-triggered storage register
The information on the D inputs is transferred to storage
during the LOW-to-HIGH clock transition The device has a
Master Reset to simultaneously clear all flip-flops
Features
Y Edge-triggered D-type inputs
Y Buffered positive edge-triggered clock
Y Asynchronous common reset
Y Guaranteed 4000V minimum ESD protection
Commercial
74F174PC
74F174SC (Note 1)
74F174SJ (Note 1)
Military
54F174DM (Note 2)
54F174FM (Note 2)
54F174LM (Note 2)
Package
Number
N16E
J16A
M16A
M16D
W16A
E20A
Package Description
16-Lead (0 300 Wide) Molded Dual-In-Line
16-Lead Ceramic Dual-In-Line
16-Lead (0 150 Wide) Molded Small Outline JEDEC
16-Lead (0 300 Wide) Molded Small Outline EIAJ
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use Suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbols
Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9489–3
IEEE IEC
TL F 9489 – 1
TL F 9489 – 2
TL F 9489–5
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9489
RRD-B30M75 Printed in U S A



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74F174SJ pdf
Unit Loading Fan Out
Pin Names
Description
D0 – D5
CP
MR
Q0 – Q5
Data Inputs
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active LOW)
Outputs
54F 74F
UL
HIGH LOW
10 10
10 10
10 10
50 33 3
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b1 mA 20 mA
Functional Description
The ’F174 consists of six edge-triggered D flip-flops with
individual D inputs and Q outputs The Clock (CP) and Mas-
ter Reset (MR) are common to all flip-flops Each D input’s
state is transferred to the corresponding flip-flop’s output
following the LOW-to-HIGH Clock (CP) transition A LOW
input to the Master Reset (MR) will force all outputs LOW
independent of Clock or Data inputs The ’F174 is useful for
applications where the true output only is required and the
Clock and Master Reset are common to all storage ele-
ments
Logic Diagram
Truth Table
Inputs
MR CP Dn
L XX
H LH
H LL
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
L e LOW-to-HIGH Clock Transition
Outputs
Qn
L
H
L
TL F 9489 – 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2



Part Number 74F174SJ
Description Hex D Flip-Flop with Master Reset
Maker National Semiconductor - National Semiconductor
Total Page 8 Pages
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