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4-Stage Synchronous Bidirectional Counter

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74F169 pdf
November 1994
54F 74F169
4-Stage Synchronous Bidirectional Counter
General Description
The ’F169 is a fully synchronous 4-stage up down counter
The ’F169 is a modulo-16 binary counter Features a preset
capability for programmable operation carry lookahead for
easy cascading and a U D input to control the direction of
counting All state changes whether in counting or parallel
loading are initiated by the LOW-to-HIGH transition of the
Y Asynchronous counting and loading
Y Built-in lookahead carry capability
Y Presettable for programmable operation
74F169SC (Note 1)
74F169SJ (Note 1)
54F169DM (Note 2)
Package Description
16-Lead (0 300 Wide) Molded Dual-In-Line
16-Lead Ceramic Dual-In-Line
16-Lead (0 150 Wide) Molded Small Outline JEDEC
16-Lead (0 300 Wide) Molded Small Outline EIAJ
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB
Logic Symbols
TL F 9488 – 3
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9488
TL F 9488 – 9
RRD-B30M75 Printed in U S A

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74F169 pdf
Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9488–1
Unit Loading Fan Out
Pin Names
P0 – P3
Q0 – Q3
Count Enable Parallel Input (Active LOW)
Count Enable Trickle Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Parallel Data Inputs
Parallel Enable Input (Active LOW)
Up-Down Count Control Input
Flip-Flop Outputs
Terminal Count Output (Active LOW)
54F 74F
10 10
10 20
10 10
10 10
10 10
10 10
50 33 3
50 33 3
Output IOH IOL
20 mA b0 6 mA
20 mA b1 2 mA
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b1 mA 20 mA
b1 mA 20 mA
TL F 9488 – 2
Functional Description
The ’F169 uses edge-triggered J-K type flip-flops and has
no constraints on changing the control or data input signals
in either state of the clock The only requirement is that the
various inputs attain the desired state at least a setup time
before the rising edge of the clock and remain valid for the
recommended hold time thereafter The parallel load opera-
tion takes precedence over other operations as indicated in
the Mode Select Table When PE is LOW the data on the
P0 – P3 inputs enters the flip-flops on the next rising edge of
the clock In order for counting to occur both CEP and CET
must be LOW and PE must be HIGH the U D input then
determines the direction of counting The Terminal Count
(TC) output is normally HIGH and goes LOW provided that
CET is LOW when a counter reaches zero in the Count
Down mode or reaches 15 for the ’F169 in the Count Up
mode The TC output state is not a function of the Count
Enable Parallel (CEP) input level Since the TC signal is de-
rived by decoding the flip-flop states there exists the possi-
bility of decoding spikes on TC For this reason the use of
TC as a clock signal is not recommended (see logic equa-
tions below)
1) Count Enable e CEP  CET  PE
2) Up (’F169) TC e Q0  Q1  Q2  Q3  (Up)  CET
3) Down TC e Q0  Q1  Q2  Q3  (Down)  CET

Part Number 74F169
Description 4-Stage Synchronous Bidirectional Counter
Maker National Semiconductor - National Semiconductor
Total Page 8 Pages
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