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National Semiconductor Electronic Components Datasheet


74F164APC

Serial-In/ Parallel-Out Shift Register



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74F164APC pdf
January 1995
54F 74F164A
Serial-In Parallel-Out Shift Register
General Description
The ’F164A is a high-speed 8-bit serial-in parallel-out shift
register Serial data is entered through a 2-input AND gate
synchronous with the LOW-to-HIGH transition of the clock
The device features an asynchronous Master Reset which
clears the register setting all outputs LOW independent of
the clock The ’F164A is a faster version of the ’F164
Features
Y Typical shift frequency of 90 MHz
Y Asynchronous Master Reset
Y Gated serial data input
Y Fully synchronous data transfers
Y Guaranteed 4000V min ESD protection
Y ’F164A is a faster version of the ’F164
Commercial
Military
Package
Number
Package Description
74F164APC
N14A
14-Lead (0 300 Wide) Molded Dual-In-Line
54F164ADM (Note 2) J14A
14-Lead Ceramic Dual-In-Line
74F164ASC (Note 1)
M14A
14-Lead (0 150 Wide) Molded Small Outline JEDEC
74F164ASJ (Note 1)
M14D
14-Lead (0 300 Wide) Molded Small Outline EIAJ
74F164AFM (Note 2) W14B
14-Lead Cerpack
74F164ALM (Note 2) E20A
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbols
IEEE IEC
TL F 10613 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 10613
TL F 10613 – 4
RRD-B30M75 Printed in U S A



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74F164APC pdf
Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 10613–2
Unit Loading Fan Out
Pin Names
Description
AB
CP
MR
Q0 – Q7
Data Inputs
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active LOW)
Outputs
54F 74F
UL
HIGH LOW
10 10
10 10
10 10
50 33 3
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b1 mA 20 mA
TL F 10613 – 3
Functional Description
The ’F164A is an edge-triggered 8-bit shift register with seri-
al data entry and an output from each of the eight stages
Data is entered serially through one of two inputs (A or B)
either of these inputs can be used as an active HIGH En-
able for data entry through the other input An unused input
must be tied HIGH
Each LOW-to-HIGH transition on the Clock (CP) input shifts
data one place to the right and enters into Q0 the logical
AND of the two data inputs (A  B) that existed before the
rising clock edge A LOW level on the Master Reset (MR)
input overrides all other inputs and clears the register asyn-
chronously forcing all Q outputs LOW
Logic Diagram
Mode Select Table
Operating
Mode
Reset (Clear)
Inputs
MR A
LX
B
X
Outputs
Q0 Q1 – Q7
L L-L
Shift
H l l L q0 – q6
H l h L q0 – q6
H h l L q0 – q6
H h h H q0 – q6
H(h) e HIGH Voltage Levels
L(l) e LOW Voltage Levels
X e Immaterial
qn e Lower case letters indicate the state of the referenced input or output
one setup time prior to the LOW-to-HIGH clock transition
TL F 10613 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2



Part Number 74F164APC
Description Serial-In/ Parallel-Out Shift Register
Maker National Semiconductor - National Semiconductor
Total Page 8 Pages
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