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National Semiconductor Electronic Components Datasheet


74C165

Parallel-Load 8-Bit Shift Register



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74C165 pdf
December 1992
MM54C165 MM74C165
Parallel-Load 8-Bit Shift Register
General Description
The MM54C165 MM74C165 functions as an 8-bit parallel-
load serial shift register Data is loaded into the register
independent of the state of the clock(s) when PARALLEL
LOAD (PL) is low Shifting is inhibited as long as PL is low
Data is sequentially shifted from complementary outputs Q7
and Q7 highest-order bit (P7) first New serial data may be
entered via the SERIAL DATA (Ds) input Serial shifting oc-
curs on the rising edge of CLOCK1 or CLOCK2 Clock in-
puts may be used separately or together for combined
clocking from independent sources Either clock input may
be used also as an active-low clock enable To prevent dou-
ble-clocking when a clock input is used as an enable the
enable must be changed to a high level (disabled) only while
the clock is high
Features
Y Wide supply voltage range
Y Guaranteed noise margin
Y High noise immunity
Y Low power TTL compatibility
Y Parallel loading independent of clock
Y Dual clock inputs
Y Fully static operation
3V to 15V
1V
0 45 VCC (typ )
fan out of 2
driving 74L
Connection and Block Diagrams
Dual-In-Line Package
Top View
TL F 5897 – 2
Order Number MM54C165 or MM74C165
Please look into Section 8 Appendix D
for availability of various package types
TL F 5897 – 1
C1995 National Semiconductor Corporation TL F 5897
TL F 5897 – 3
RRD-B30M105 Printed in U S A



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74C165 pdf
Absolute Maximum Ratings (Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Voltage at Any Pin
Operating Temperature Range
MM54C165
MM74C165
b0 3V to VCCa0 3V
b55 C to a125 C
b40 C to a85 C
Storage Temperature Range
Absolute Maximum VCC
Power Dissipation
Dual-In-Line
Small Outline
Operating VCC Range
Lead Temperature (Soldering 10 sec )
b65 C to a150 C
18V
700 mW
500 mW
3V to 15V
260 C
DC Electrical Characteristics Min Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min Typ Max Units
CMOS TO CMOS
VIN(1)
Logical ‘‘1’’ Input Voltage
VIN(0)
Logical ‘‘0’’ Input Voltage
VOUT(1)
Logical ‘‘1’’ Output Voltage
VOUT(0)
Logical ‘‘0’’ Output Voltage
IIN(1)
Logical ‘‘1’’ Input Current
IIN(0)
Logical ‘‘0’’ Input Current
ICC Supply Current
CMOS TO LPTTL INTERFACE
VCC e 5V
VCC e 10V
VCC e 5V
VCC e 10V
VCC e 5V IO e b10 mA
VCC e 10V IO e b10 mA
VCC e 5V IO e a10 mA
VCC e 10V IO e a10 mA
VCC e 15V VIN e 15V
VCC e 15V VIN e 0V
VCC e 15V
35
80
45
90
b1 0
15
20
0 005
b0 005
0 05
05
10
10
300
V
V
V
V
V
V
V
V
mA
mA
mA
VIN(1)
Logical ‘‘1’’ Input Voltage
54C VCC e 4 5V
74C VCC e 4 75V
VCC b 1 5
VCC b 1 5
VIN(0)
Logical ‘‘0’’ Input Voltage
54C VCC e 4 5V
74C VCC e 4 75V
VOUT(1)
Logical ‘‘1’’ Output Voltage
54C VCC e 4 5V IO e b360 mA
74C VCC e 4 75V IO e b360 mA
24
24
VOUT(0)
Logical ‘‘0’’ Output Voltage
54C VCC e 4 5V IO e 360 mA
74C VCC e 4 75V IO e 360 mA
OUTPUT DRIVE (See 54C 74C Family Characteristics Data Sheet) (short circuit current)
V
V
08 V
08 V
V
V
04 V
04 V
ISOURCE
Output Source Current
(P-Channel)
VCC e 5V
TA e 25 C VOUT e 0V
b1 75
b3 3
mA
ISOURCE
Output Source Current
(P-Channel)
VCC e 10V
TA e 25 C VOUT e 0V
b8 0
b15
mA
ISINK
Output Sink Current
(N-Channel)
VCC e 5V
TA e 25 C VOUT e VCC
1 75 3 6
mA
ISINK
Output Sink Current
(N-Channel)
VCC e 10V
TA e 25 C VOUT e VCC
8 0 16
mA
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation
2



Part Number 74C165
Description Parallel-Load 8-Bit Shift Register
Maker National Semiconductor - National Semiconductor
Total Page 6 Pages
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