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National Semiconductor Electronic Components Datasheet


74AC899

9-Bit Latchable Transceiver



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74AC899 pdf
August 1994
74AC899  54ACT 74ACT899
9-Bit Latchable Transceiver
with Parity Generator Checker
General Description
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The ’AC ’ACT899 is a 9-bit to 9-bit parity transceiver with
transparent latches The device can operate as a feed-
through transceiver or it can generate check parity from the
8-bit data busses in either direction The ’AC ’ACT899 fea-
tures independent latch enables for the A-to-B direction and
the B-to-A direction a select pin for ODD EVEN parity and
separate error signal output pins for checking parity
Features
Y Latchable transceiver with output sink of 24 mA
Y Option to select generate parity and check or ‘‘feed-
through’’ data parity in directions A-to-B or B-to-A
Y Independent latch enable for A-to-B and B-to-A direc-
tions
Y Select pin for ODD EVEN parity
Y ERRA and ERRB output pins for parity checking
Y Ability to simultaneously generate and check parity
Y May be used in system applications in place of the ’280
Y May be used in system applications in place of the ’657
and ’373 (no need to change T R to check parity)
Y 4 kV minimum ESD immunity
Logic Symbol
Connection Diagram
Pin Assignment for PCC and LCC
TL F 10637 – 1
TL F 10637 – 2
TRI-STATE is a registered trademark of National Semiconductor Corporation
FACTTM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 10637
RRD-B30M75 Printed in U S A



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Pin Names
A0 – A7
B0 – B7
APAR BPAR
ODD EVEN
GBA GAB
SEL
LEA LEB
ERRA ERRB
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Description
A Bus Data Inputs Data Outputs
B Bus Data Inputs Data Outputs
A and B Bus Parity Inputs
ODD EVEN Parity Select Active
LOW for EVEN Parity
Output Enables for A or B Bus
Active LOW
Select Pin for Feed-Through or
Generate Mode LOW for Generate
Mode
Latch Enables for A and B Latches
HIGH for Transparent Mode
Error Signals for Checking
Generated Parity with Parity In
LOW if Error Occurs
Functional Description
The ’AC ’ACT899 has three principal modes of operation
which are outlined below These modes apply to both the A-
to-B and B-to-A directions
Bus A (B) communicates to Bus B (A) parity is generat-
ed and passed on to the B (A) Bus as BPAR (APAR) If
LEB (LEA) is HIGH and the Mode Select (SEL) is LOW
the parity generated from B 0 7 (A 0 7 ) can be
checked and monitored by ERRB (ERRA)
Bus A (B) communicates to Bus B (A) in a feed-through
mode if SEL is HIGH Parity is still generated and
checked as ERRA and ERRB in the feed-through mode
(can be used as an interrupt to signal a data parity bit
error to the CPU)
Independent Latch Enables (LEA and LEB) allow other
permutations of generating checking (see Function Ta-
ble below)
Function Table
Inputs
GAB GBA SEL LEA LEB
Operation
H H X X X Busses A and B are TRI-STATE
H L L L H Generates parity from B 0 7 based on O E (Note 1) Generated parity
x APAR Generated parity checked against BPAR and output as
ERRB
xH L L H H Generates parity from B 0 7 based on O E Generated parity
APAR Generated parity checked against BPAR and output as ERRB
Generated parity also fed back through the A latch for generate check
as ERRA
H L L X L Generates parity from B latch data based on O E Generated parity
x APAR Generated parity checked against latched BPAR and
output as ERRB
xH L H X H BPAR B 0 7
APAR A0 7 Feed-through mode Generated parity
checked against BPAR and output as ERRB
xH L H H H BPAR B 0 7
APAR A 0 7
Feed-through mode Generated parity checked against BPAR and
output as ERRB Generated parity also fed back through the A latch for
generate check as ERRA
xL H L H L Generates parity for A 0 7 based on O E Generated parity
BPAR Generated parity checked against APAR and output as ERRA
xL H L H H Generates parity from A 0 7 based on O E Generated parity
BPAR Generated parity checked against APAR and output as ERRA
Generated parity also fed back through the B latch for generate check
as ERRB
L H L L X Generates parity from A latch data based on O E Generated parity
x BPAR Generated parity checked against latched APAR and
output as ERRA
xL H H H L APAR A 0 7
BPAR B 0 7
Feed-through mode Generated parity checked against APAR and
output as ERRA
xL H H H H APAR A 0 7
BPAR B 0 7
Feed-through mode Generated parity checked against APAR and
output as ERRA Generated parity also fed back through the B latch for
generate check as ERRB
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Note 1 O E e ODD EVEN
2



Part Number 74AC899
Description 9-Bit Latchable Transceiver
Maker National Semiconductor - National Semiconductor
Total Page 14 Pages
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