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4-Stage Synchronous Bidirectional Counter

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74AC169 pdf
April 1993
54AC 74AC16954ACT 74ACT169
4-Stage Synchronous Bidirectional Counter
General Description
The ’AC ’ACT169 is fully synchronous 4-stage up down
counter The ’AC ’ACT169 is a modulo-16 binary counter It
features a preset capability for programmable operation
carry lookahead for easy cascading and a U D input to con-
trol the direction of counting All state changes whether in
counting or parallel loading are initiated by the LOW-to-
HIGH transition of the Clock
Y ICC reduced by 50%
Y Synchronous counting and loading
Y Built-In lookahead carry capability
Y Presettable for programmable operation
Y Outputs source sink 24 mA
Y ’ACT has TTL-compatible inputs
Y Standard Military Drawing (SMD)
’AC169 5962-91603
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP Flatpak and SOIC
TL F 9934–1
Pin Names
P0 – P3
Q0 – Q3
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
Parallel Data Inputs
Parallel Enable Input
Up-Down Count Control Input
Flip-Flop Outputs
Terminal Count Output
FACTTM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9934
TL F 9934 – 2
TL F 9934 – 3
Pin Assignment
for LCC
TL F 9934 – 4
RRD-B30M75 Printed in U S A

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74AC169 pdf
Logic Diagram
TL F 9934 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
Functional Description
The ’AC ’ACT169 uses edge-triggered J-K-type flip-flops
and have no constraints on changing the control or data
input signals in either state of the Clock The only require-
ment is that the various inputs attain the desired state at
least a setup time before the rising edge of the clock and
remain valid for the recommended hold time thereafter The
parallel load operation takes precedence over the other op-
erations as indicated in the Mode Select Table When PE is
LOW the data on the P0 – P3 inputs enters the flip-flops on
the next rising edge of the Clock In order for counting to
occur both CEP and CET must be LOW and PE must be
HIGH the U D input then determines the direction of count-
ing The Terminal Count (TC) output is normally HIGH and
goes LOW provided that CET is LOW when a counter
reaches zero in the Count Down mode or reaches 15 in the
Count Up mode The TC output state is not a function of the
Count Enable Parallel (CEP) input level If an illegal state
occurs the ’AC169 will return to the legitimate sequence
within two counts Since the TC signal is derived by decod-
ing the flip-flop states there exists the possibility of decod-
ing spikes on TC For this reason the use of TC as a clock
signal is not recommended (see logic equations below)
1) Count Enable e CEPCETPE
2) Up TC e Q0Q1Q2Q3(Up)CET
3) Down TC e Q0Q1Q2Q3(Down)CET
Mode Select Table
Action on Rising
Clock Edge
L X X X Load (Pn to Qn)
H L L H Count Up (Increment)
H L L L Count Down (Decrement)
H H X X No Change (Hold)
H X H X No Change (Hold)
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
State Diagrams
TL F 9934 – 6

Part Number 74AC169
Description 4-Stage Synchronous Bidirectional Counter
Maker National Semiconductor - National Semiconductor
Total Page 12 Pages
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