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74ABT16374B

16-bit D-type flip-flop; positive-edge trigger 3-State



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74ABT16374B pdf
INTEGRATED CIRCUITS
74ABT16374B
74ABTH16374B
16-bit D-type flip-flop;
positive-edge trigger (3-State)
Product specification
Supersedes data of 1995 Sep 28
IC23 Data Handbook
1998 Feb 27
Philips
Semiconductors



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74ABT16374B pdf
Philips Semiconductors
16-bit D-type flip-flop; positive-edge trigger
(3-State)
Product specification
74ABT16374B
74ABTH16374B
FEATURES
Two 8-bit positive edge triggered registers
Live insertion/extraction permitted
Power-up 3-State
Power-up reset
Multiple VCC and GND pins minimize switching noise
3-State output buffers
74ABTH16373B incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Output capability: +64mA/–32mA
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH
tPHL
CIN
COUT
ICCZ
ICCL
Propagation delay
nCP to nQx
Input capacitance
Output capacitance
Quiescent supply current
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
DESCRIPTION
The 74ABT16374B high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16374B has two 8-bit, edge triggered registers, with each
register coupled to eight 3-State output buffers. The two sections of
each register are controlled independently by the clock (nCP) and
Output Enable (nOE) control gates.
Each register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. Each
active-Low Output Enable (nOE) controls all eight 3-State buffers for
its register independent of the clock operation.
When nOE is Low, the stored data appears at the outputs for that
register. When nOE is High, the outputs for that register are in the
High-impedance “OFF” state, which means they will neither drive
nor load the bus.
Two options are available, 74ABT16374B which does not have the
bus-hold feature and 74ABTH16374B which incorporates the
bus-hold feature.
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF; VCC = 5V
VI = 0V or VCC
VO = 0V or VCC; 3-State
Outputs disabled; VCC = 5.5V
Outputs Low; VCC = 5.5V
TYPICAL
2.6
2.2
4
7
500
8
UNIT
ns
pF
pF
µA
mA
OUTSIDE NORTH AMERICA
74ABT16374B DL
74ABT16374B DGG
74ABTH16374B DL
74ABTH16374B DGG
NORTH AMERICA
BT16374B DL
BT16374B DGG
BH16374B DL
BH16374B DGG
DWG NUMBER
SOT370-1
SOT362-1
SOT370-1
SOT362-1
PIN DESCRIPTION
LOGIC SYMBOL
PIN NUMBER
47, 46, 44, 43, 41, 40, 38, 37
36, 35, 33, 32, 30, 29, 27, 26
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20, 22, 23
1, 24
SYMBOL
FUNCTION
1D0 – 1D7
2D0 – 2D7
Data inputs
1Q0 – 1Q7
2Q0 – 2Q7
Data outputs
1OE, 2OE
Output enable
inputs (active-Low)
47 46 44 43 41 40 38 37
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7
48 1CP
1 1OE
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
48, 25
4, 10, 15, 21, 28, 34, 39, 45
1CP, 2CP
GND
Clock pulse inputs
(active rising edge)
Ground (0V)
2 3 5 6 8 9 11 12
36 35 33 32 30 29 27 26
7, 18, 31, 42
VCC
Positive supply
voltage
2D0 2D21 2D2 2D3 2D4 2D5 2D6 2D7
25 2CP
24 2OE
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
1998 Feb 27
13 14 16 17 19 20 22 23
SH00078
2 853-1752 19027



Part Number 74ABT16374B
Description 16-bit D-type flip-flop; positive-edge trigger 3-State
Maker NXP - NXP
Total Page 10 Pages
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